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target/arm: Implement PIR_ELx, PIRE0_ELx, S2PIR_EL2 registers

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Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20251008215613.300150-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2025-10-08 14:55:04 -07:00 • committed by Peter Maydell
parent 48669f526d
commit 0277e0652b
4 changed files with 79 additions and 0 deletions
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2
target/arm/cpregs.h
View file

@ -781,6 +781,8 @@ typedef enum FGTBit {
DO_BIT(HFGRTR, ERRIDR_EL1),
DO_REV_BIT(HFGRTR, NSMPRI_EL1),
DO_REV_BIT(HFGRTR, NTPIDR2_EL0),
DO_REV_BIT(HFGRTR, NPIRE0_EL1),
DO_REV_BIT(HFGRTR, NPIR_EL1),
/* Trap bits in HDFGRTR_EL2 / HDFGWTR_EL2, starting from bit 0. */
DO_BIT(HDFGRTR, DBGBCRN_EL1),

4
target/arm/cpu.c
View file

@ -641,6 +641,10 @@ void arm_emulate_firmware_reset(CPUState *cpustate, int target_el)
if (cpu_isar_feature(aa64_sctlr2, cpu)) {
env->cp15.scr_el3 |= SCR_SCTLR2EN;
}
if (cpu_isar_feature(aa64_s1pie, cpu) ||
cpu_isar_feature(aa64_s2pie, cpu)) {
env->cp15.scr_el3 |= SCR_PIEN;
}
}
if (target_el == 2) {

4
target/arm/cpu.h
View file

@ -368,6 +368,9 @@ typedef struct CPUArchState {
uint64_t tcr2_el[3];
uint64_t vtcr_el2; /* Virtualization Translation Control. */
uint64_t vstcr_el2; /* Secure Virtualization Translation Control. */
uint64_t pir_el[4]; /* PIRE0_EL1, PIR_EL1, PIR_EL2, PIR_EL3 */
uint64_t pire0_el2;
uint64_t s2pir_el2;
uint32_t c2_data; /* MPU data cacheable bits. */
uint32_t c2_insn; /* MPU instruction cacheable bits. */
union { /* MMU domain access control register
@ -1720,6 +1723,7 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
#define SCR_ENTP2 (1ULL << 41)
#define SCR_TCR2EN (1ULL << 43)
#define SCR_SCTLR2EN (1ULL << 44)
#define SCR_PIEN (1ULL << 45)
#define SCR_GPF (1ULL << 48)
#define SCR_NSE (1ULL << 62)

69
target/arm/helper.c
View file

@ -770,6 +770,10 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
if (cpu_isar_feature(aa64_sctlr2, cpu)) {
valid_mask |= SCR_SCTLR2EN;
}
if (cpu_isar_feature(aa64_s1pie, cpu) ||
cpu_isar_feature(aa64_s2pie, cpu)) {
valid_mask |= SCR_PIEN;
}
} else {
valid_mask &= ~(SCR_RW | SCR_ST);
if (cpu_isar_feature(aa32_ras, cpu)) {
@ -5941,6 +5945,64 @@ static const ARMCPRegInfo tcr2_reginfo[] = {
.fieldoffset = offsetof(CPUARMState, cp15.tcr2_el[2]) },
};
static CPAccessResult pien_access(CPUARMState *env, const ARMCPRegInfo *ri,
bool isread)
{
if (arm_feature(env, ARM_FEATURE_EL3)
&& !(env->cp15.scr_el3 & SCR_PIEN)
&& arm_current_el(env) < 3) {
return CP_ACCESS_TRAP_EL3;
}
return CP_ACCESS_OK;
}
static CPAccessResult pien_el1_access(CPUARMState *env, const ARMCPRegInfo *ri,
bool isread)
{
CPAccessResult ret = access_tvm_trvm(env, ri, isread);
if (ret == CP_ACCESS_OK) {
ret = pien_access(env, ri, isread);
}
return ret;
}
static const ARMCPRegInfo s1pie_reginfo[] = {
{ .name = "PIR_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .opc2 = 3, .crn = 10, .crm = 2,
.access = PL1_RW, .accessfn = pien_el1_access,
.fgt = FGT_NPIR_EL1, .nv2_redirect_offset = 0x2a0 | NV2_REDIR_NV1,
.vhe_redir_to_el2 = ENCODE_AA64_CP_REG(3, 4, 10, 2, 3),
.vhe_redir_to_el01 = ENCODE_AA64_CP_REG(3, 5, 10, 2, 3),
.fieldoffset = offsetof(CPUARMState, cp15.pir_el[1]) },
{ .name = "PIR_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .opc2 = 3, .crn = 10, .crm = 2,
.access = PL2_RW, .accessfn = pien_access,
.fieldoffset = offsetof(CPUARMState, cp15.pir_el[2]) },
{ .name = "PIR_EL3", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 6, .opc2 = 3, .crn = 10, .crm = 2,
.access = PL3_RW,
.fieldoffset = offsetof(CPUARMState, cp15.pir_el[3]) },
{ .name = "PIRE0_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 10, .crm = 2,
.access = PL1_RW, .accessfn = pien_el1_access,
.fgt = FGT_NPIRE0_EL1, .nv2_redirect_offset = 0x290 | NV2_REDIR_NV1,
.vhe_redir_to_el2 = ENCODE_AA64_CP_REG(3, 4, 10, 2, 2),
.vhe_redir_to_el01 = ENCODE_AA64_CP_REG(3, 5, 10, 2, 2),
.fieldoffset = offsetof(CPUARMState, cp15.pir_el[0]) },
{ .name = "PIRE0_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .opc2 = 2, .crn = 10, .crm = 2,
.access = PL2_RW, .accessfn = pien_access,
.fieldoffset = offsetof(CPUARMState, cp15.pire0_el2) },
};
static const ARMCPRegInfo s2pie_reginfo[] = {
{ .name = "S2PIR_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .opc2 = 5, .crn = 10, .crm = 2,
.access = PL2_RW, .accessfn = pien_access,
.nv2_redirect_offset = 0x2b0,
.fieldoffset = offsetof(CPUARMState, cp15.s2pir_el2) },
};
void register_cp_regs_for_features(ARMCPU *cpu)
{
/* Register all the coprocessor registers based on feature bits */
@ -7173,6 +7235,13 @@ void register_cp_regs_for_features(ARMCPU *cpu)
define_arm_cp_regs(cpu, tcr2_reginfo);
}
if (cpu_isar_feature(aa64_s1pie, cpu)) {
define_arm_cp_regs(cpu, s1pie_reginfo);
}
if (cpu_isar_feature(aa64_s2pie, cpu)) {
define_arm_cp_regs(cpu, s2pie_reginfo);
}
if (cpu_isar_feature(any_predinv, cpu)) {
define_arm_cp_regs(cpu, predinv_reginfo);
}