Testing infrastructure for softfpu (not run by default).
Drop countLeadingZeros. Fix div_floats. Add udiv_qrnnd specializations for x86_64, s390x, ppc64 hosts. -----BEGIN PGP SIGNATURE----- iQEcBAABAgAGBQJbt6apAAoJEGTfOOivfiFfv7IH/2pFUMKB8aaFA6p4xlMCufYg usYvyXqul2D6/ZFwirsxOmFrVs0Vx8/E2BHMvW7fx+XVfMUa7bUNYKeYwTtvKgI1 hsm1hKEedVl+hOLZZBfiPEbMnm5Epg2L2NbLpMo1RWWqqKjlOMMU0RZH/lBpuoT3 OUDQEQaMvTC91xqhWDgwkedNGRl57kXNDYLQAvfhYtcKHj8vYgwbzA46/y1p1xVd E37ym5jL6DHhzIoU7ty9u74PxkM2qBKGhVlRqLQ0YO6gStKoW0ZBVZSlQx9NPG7J OjYYmZwWs5T61ai0e3N0sqP5QJyhs7g/FfmKDgzhPMFkeGh8kwihjdJwPaKzJ88= =iTHi -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/rth/tags/pull-fpu-20181005' into staging Testing infrastructure for softfpu (not run by default). Drop countLeadingZeros. Fix div_floats. Add udiv_qrnnd specializations for x86_64, s390x, ppc64 hosts. # gpg: Signature made Fri 05 Oct 2018 19:00:09 BST # gpg: using RSA key 64DF38E8AF7E215F # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-fpu-20181005: softfloat: Specialize udiv_qrnnd for ppc64 softfloat: Specialize udiv_qrnnd for s390x softfloat: Specialize udiv_qrnnd for x86_64 softfloat: Fix division softfloat: Replace countLeadingZeros32/64 with clz32/64 tests/fp/fp-test: add floating point tests gitmodules: add berkeley's softfloat + testfloat version 3 softfloat: remove float64_trunc_to_int Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
079911cb6e
13 changed files with 2392 additions and 125 deletions
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@ -79,17 +79,6 @@ this code that are retained.
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* version 2 or later. See the COPYING file in the top-level directory.
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*/
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/*----------------------------------------------------------------------------
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| This macro tests for minimum version of the GNU C compiler.
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*----------------------------------------------------------------------------*/
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#if defined(__GNUC__) && defined(__GNUC_MINOR__)
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# define SOFTFLOAT_GNUC_PREREQ(maj, min) \
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((__GNUC__ << 16) + __GNUC_MINOR__ >= ((maj) << 16) + (min))
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#else
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# define SOFTFLOAT_GNUC_PREREQ(maj, min) 0
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#endif
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/*----------------------------------------------------------------------------
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| Shifts `a' right by the number of bits given in `count'. If any nonzero
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| bits are shifted off, they are ``jammed'' into the least significant bit of
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@ -340,15 +329,30 @@ static inline void
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| pieces which are stored at the locations pointed to by `z0Ptr' and `z1Ptr'.
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*----------------------------------------------------------------------------*/
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static inline void
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shortShift128Left(
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uint64_t a0, uint64_t a1, int count, uint64_t *z0Ptr, uint64_t *z1Ptr)
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static inline void shortShift128Left(uint64_t a0, uint64_t a1, int count,
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uint64_t *z0Ptr, uint64_t *z1Ptr)
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{
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*z1Ptr = a1 << count;
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*z0Ptr = count == 0 ? a0 : (a0 << count) | (a1 >> (-count & 63));
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}
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*z1Ptr = a1<<count;
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*z0Ptr =
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( count == 0 ) ? a0 : ( a0<<count ) | ( a1>>( ( - count ) & 63 ) );
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/*----------------------------------------------------------------------------
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| Shifts the 128-bit value formed by concatenating `a0' and `a1' left by the
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| number of bits given in `count'. Any bits shifted off are lost. The value
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| of `count' may be greater than 64. The result is broken into two 64-bit
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| pieces which are stored at the locations pointed to by `z0Ptr' and `z1Ptr'.
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*----------------------------------------------------------------------------*/
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static inline void shift128Left(uint64_t a0, uint64_t a1, int count,
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uint64_t *z0Ptr, uint64_t *z1Ptr)
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{
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if (count < 64) {
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*z1Ptr = a1 << count;
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*z0Ptr = count == 0 ? a0 : (a0 << count) | (a1 >> (-count & 63));
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} else {
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*z1Ptr = 0;
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*z0Ptr = a1 << (count - 64);
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}
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}
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/*----------------------------------------------------------------------------
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@ -630,8 +634,36 @@ static inline uint64_t estimateDiv128To64(uint64_t a0, uint64_t a1, uint64_t b)
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*
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* Licensed under the GPLv2/LGPLv3
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*/
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static inline uint64_t div128To64(uint64_t n0, uint64_t n1, uint64_t d)
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static inline uint64_t udiv_qrnnd(uint64_t *r, uint64_t n1,
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uint64_t n0, uint64_t d)
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{
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#if defined(__x86_64__)
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uint64_t q;
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asm("divq %4" : "=a"(q), "=d"(*r) : "0"(n0), "1"(n1), "rm"(d));
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return q;
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#elif defined(__s390x__)
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/* Need to use a TImode type to get an even register pair for DLGR. */
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unsigned __int128 n = (unsigned __int128)n1 << 64 | n0;
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asm("dlgr %0, %1" : "+r"(n) : "r"(d));
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*r = n >> 64;
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return n;
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#elif defined(_ARCH_PPC64)
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/* From Power ISA 3.0B, programming note for divdeu. */
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uint64_t q1, q2, Q, r1, r2, R;
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asm("divdeu %0,%2,%4; divdu %1,%3,%4"
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: "=&r"(q1), "=r"(q2)
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: "r"(n1), "r"(n0), "r"(d));
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r1 = -(q1 * d); /* low part of (n1<<64) - (q1 * d) */
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r2 = n0 - (q2 * d);
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Q = q1 + q2;
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R = r1 + r2;
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if (R >= d || R < r2) { /* overflow implies R > d */
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Q += 1;
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R -= d;
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}
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*r = R;
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return Q;
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#else
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uint64_t d0, d1, q0, q1, r1, r0, m;
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d0 = (uint32_t)d;
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@ -669,8 +701,9 @@ static inline uint64_t div128To64(uint64_t n0, uint64_t n1, uint64_t d)
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}
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r0 -= m;
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/* Return remainder in LSB */
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return (q1 << 32) | q0 | (r0 != 0);
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*r = r0;
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return (q1 << 32) | q0;
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#endif
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}
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/*----------------------------------------------------------------------------
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@ -712,82 +745,6 @@ static inline uint32_t estimateSqrt32(int aExp, uint32_t a)
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}
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/*----------------------------------------------------------------------------
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| Returns the number of leading 0 bits before the most-significant 1 bit of
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| `a'. If `a' is zero, 32 is returned.
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*----------------------------------------------------------------------------*/
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static inline int8_t countLeadingZeros32(uint32_t a)
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{
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#if SOFTFLOAT_GNUC_PREREQ(3, 4)
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if (a) {
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return __builtin_clz(a);
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} else {
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return 32;
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}
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#else
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static const int8_t countLeadingZerosHigh[] = {
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8, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4,
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3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
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};
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int8_t shiftCount;
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shiftCount = 0;
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if ( a < 0x10000 ) {
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shiftCount += 16;
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a <<= 16;
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}
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if ( a < 0x1000000 ) {
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shiftCount += 8;
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a <<= 8;
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}
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shiftCount += countLeadingZerosHigh[ a>>24 ];
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return shiftCount;
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#endif
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}
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/*----------------------------------------------------------------------------
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| Returns the number of leading 0 bits before the most-significant 1 bit of
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| `a'. If `a' is zero, 64 is returned.
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*----------------------------------------------------------------------------*/
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static inline int8_t countLeadingZeros64(uint64_t a)
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{
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#if SOFTFLOAT_GNUC_PREREQ(3, 4)
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if (a) {
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return __builtin_clzll(a);
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} else {
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return 64;
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}
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#else
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int8_t shiftCount;
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shiftCount = 0;
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if ( a < ( (uint64_t) 1 )<<32 ) {
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shiftCount += 32;
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}
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else {
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a >>= 32;
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}
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shiftCount += countLeadingZeros32( a );
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return shiftCount;
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#endif
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}
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/*----------------------------------------------------------------------------
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| Returns 1 if the 128-bit value formed by concatenating `a0' and `a1'
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| is equal to the 128-bit value formed by concatenating `b0' and `b1'.
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@ -535,7 +535,6 @@ float128 float64_to_float128(float64, float_status *status);
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| Software IEC/IEEE double-precision operations.
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*----------------------------------------------------------------------------*/
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float64 float64_round_to_int(float64, float_status *status);
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float64 float64_trunc_to_int(float64, float_status *status);
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float64 float64_add(float64, float64, float_status *status);
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float64 float64_sub(float64, float64, float_status *status);
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float64 float64_mul(float64, float64, float_status *status);
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