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hw/ppc: Add a test machine for the IBM PPE42 CPU

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Adds a test machine for the IBM PPE42 processor, including a
DEC, FIT, WDT and 512 KiB of ram.

The purpose of this machine is only to provide a generic platform
for testing instructions of the recently  added PPE42 processor
model which is used extensively in the IBM Power9, Power10 and
future Power server processors.

Signed-off-by: Glenn Miles <milesg@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Link: https://lore.kernel.org/r/20250925201758.652077-9-milesg@linux.ibm.com
Message-ID: <20250925201758.652077-9-milesg@linux.ibm.com>
This commit is contained in:
Glenn Miles 2025-09-25 15:17:46 -05:00 • committed by Harsh Prateek Bora
parent 7197f6f7ba
commit 0ad5b8d9c8
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GPG key ID: 4544E994F9D68FBB
4 changed files with 114 additions and 0 deletions
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6
MAINTAINERS
View file

@ -1530,6 +1530,12 @@ F: include/hw/pci-host/grackle.h
F: pc-bios/qemu_vga.ndrv
F: tests/functional/ppc/test_mac.py
PPE42
M: Glenn Miles <milesg@linux.ibm.com>
L: qemu-ppc@nongnu.org
S: Odd Fixes
F: hw/ppc/ppe42_machine.c
PReP
M: Hervé Poussineau <hpoussin@reactos.org>
L: qemu-ppc@nongnu.org

5
hw/ppc/Kconfig
View file

@ -44,6 +44,11 @@ config POWERNV
select SSI_M25P80
select PNV_SPI
config PPC405
bool
default y
depends on PPC
config PPC440
bool
default y

2
hw/ppc/meson.build
View file

@ -57,6 +57,8 @@ ppc_ss.add(when: 'CONFIG_POWERNV', if_true: files(
'pnv_n1_chiplet.c',
))
# PowerPC 4xx boards
ppc_ss.add(when: 'CONFIG_PPC405', if_true: files(
'ppe42_machine.c'))
ppc_ss.add(when: 'CONFIG_PPC440', if_true: files(
'ppc440_bamboo.c',
'ppc440_uc.c'))

101
hw/ppc/ppe42_machine.c Normal file
View file

@ -0,0 +1,101 @@
/*
* Test Machine for the IBM PPE42 processor
*
* Copyright (c) 2025, IBM Corporation.
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qemu/error-report.h"
#include "system/address-spaces.h"
#include "hw/boards.h"
#include "hw/ppc/ppc.h"
#include "system/system.h"
#include "system/reset.h"
#include "system/kvm.h"
#include "qapi/error.h"
#define TYPE_PPE42_MACHINE MACHINE_TYPE_NAME("ppe42_machine")
typedef MachineClass Ppe42MachineClass;
typedef struct Ppe42MachineState Ppe42MachineState;
DECLARE_OBJ_CHECKERS(Ppe42MachineState, Ppe42MachineClass,
PPE42_MACHINE, TYPE_PPE42_MACHINE)
struct Ppe42MachineState {
MachineState parent_obj;
PowerPCCPU cpu;
};
static void main_cpu_reset(void *opaque)
{
PowerPCCPU *cpu = opaque;
cpu_reset(CPU(cpu));
}
static void ppe42_machine_init(MachineState *machine)
{
Ppe42MachineState *pms = PPE42_MACHINE(machine);
PowerPCCPU *cpu = &pms->cpu;
if (kvm_enabled()) {
error_report("machine %s does not support the KVM accelerator",
MACHINE_GET_CLASS(machine)->name);
exit(EXIT_FAILURE);
}
if (machine->ram_size > 512 * KiB) {
error_report("RAM size more than 512 KiB is not supported");
exit(1);
}
/* init CPU */
object_initialize_child(OBJECT(pms), "cpu", cpu, machine->cpu_type);
if (!qdev_realize(DEVICE(cpu), NULL, &error_fatal)) {
return;
}
qemu_register_reset(main_cpu_reset, cpu);
/* This sets the decrementer timebase */
ppc_booke_timers_init(cpu, 37500000, PPC_TIMER_PPE);
/* RAM */
memory_region_add_subregion(get_system_memory(), 0xfff80000, machine->ram);
}
static void ppe42_machine_class_init(ObjectClass *oc, const void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
static const char * const valid_cpu_types[] = {
POWERPC_CPU_TYPE_NAME("PPE42"),
POWERPC_CPU_TYPE_NAME("PPE42X"),
POWERPC_CPU_TYPE_NAME("PPE42XM"),
NULL,
};
mc->desc = "PPE42 Test Machine";
mc->init = ppe42_machine_init;
mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("PPE42XM");
mc->valid_cpu_types = valid_cpu_types;
mc->default_ram_id = "ram";
mc->default_ram_size = 512 * KiB;
}
static const TypeInfo ppe42_machine_info = {
.name = TYPE_PPE42_MACHINE,
.parent = TYPE_MACHINE,
.instance_size = sizeof(Ppe42MachineState),
.class_init = ppe42_machine_class_init,
.class_size = sizeof(Ppe42MachineClass),
};
static void ppe42_machine_register_types(void)
{
type_register_static(&ppe42_machine_info);
}
type_init(ppe42_machine_register_types);