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hw/intc: Add (new) ASPEED VIC device model

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Implement a basic ASPEED VIC device model for the AST2400 SoC[1], with
enough functionality to boot an aspeed_defconfig Linux kernel. The model
implements the 'new' (revised) register set: While the hardware exposes
both the new and legacy register sets, accesses to the model's legacy
register set will not be serviced (however the access will be logged).

[1] http://www.aspeedtech.com/products.php?fPath=20&rId=376

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Message-id: 1458096317-25223-3-git-send-email-andrew@aj.id.au
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Andrew Jeffery 2016-03-16 17:06:00 +00:00 • committed by Peter Maydell
parent c04bd47db6
commit 0c69996e22
4 changed files with 395 additions and 0 deletions
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48
include/hw/intc/aspeed_vic.h Normal file
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/*
* ASPEED Interrupt Controller (New)
*
* Andrew Jeffery <andrew@aj.id.au>
*
* Copyright 2016 IBM Corp.
*
* This code is licensed under the GPL version 2 or later. See
* the COPYING file in the top-level directory.
*
* Need to add SVIC and CVIC support
*/
#ifndef ASPEED_VIC_H
#define ASPEED_VIC_H
#include "hw/sysbus.h"
#define TYPE_ASPEED_VIC "aspeed.vic"
#define ASPEED_VIC(obj) OBJECT_CHECK(AspeedVICState, (obj), TYPE_ASPEED_VIC)
#define ASPEED_VIC_NR_IRQS 51
typedef struct AspeedVICState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion iomem;
qemu_irq irq;
qemu_irq fiq;
uint64_t level;
uint64_t raw;
uint64_t select;
uint64_t enable;
uint64_t trigger;
/* 0=edge, 1=level */
uint64_t sense;
/* 0=single-edge, 1=dual-edge */
uint64_t dual_edge;
/* 0=low-sensitive/falling-edge, 1=high-sensitive/rising-edge */
uint64_t event;
} AspeedVICState;
#endif /* ASPEED_VIC_H */