target-arm queue:
* New board type max78000fthr * Enable use of CXL on Arm 'virt' board * Some more tidyup of ID register handling * Refactor AT insns and PMU regs into separate source files * Don't enforce NSE,NS check for EL3->EL3 returns * hw/arm/fsl-imx8mp: Wire VIRQ and VFIQ * Allow nested-virtualization with KVM on the 'virt' board * system/qdev: Remove pointless NULL check in qdev_device_add_from_qdict * hw/arm/virt-acpi-build: Don't create ITS id mappings by default * target/arm: Remove unused helper_sme2_luti4_4b -----BEGIN PGP SIGNATURE----- iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmhxEcoZHHBldGVyLm1h eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3j5yEACWYnNeqo8Yph6/EJExE6eV r0tC6FBb5ShPgA6kDxhpOc1lI6uXGh8+D7bL9BePEdz/brCf1QDfs2Z4q/hb5ysX D0H6VI5Gr1j6MjkFRBo3+vvYz4Yh++XLn5Q9lZv8zaSEdraq/ay2kxnuhRCK+4Ar +QoGtKrGMJ7UCpfiRlvNnd1UjgORZf10EE/bRImX13sxeDomP3CZhFzAyJyShOP9 JA7bAd4rYJ4oj8R33y8Yaxjwm4FOndj740B0zwpO8mpjzFiE5zbqsaO+mEgYSflc OQisCu/KRFpyIR+UqP+4gNaJLfKQW5Y4r61zEaiJWV/c4RdKNnbK1f7MX11fNhOk k1paF3GIXp6f794Hb14vtsYnKHF2eeNSmRkAomXxLgUSYzLezL+yj7cdYmRJhgYU thc1PSiEmHYhjRmOaMC9+dkMtvIexWyDNYNFTygoOE5/kTMSazeTFQpFmw+ZuTee 9pjKsYRZJgTa64IkJy1L34jc2gds48Q20KpQsqZ22KQcjwt4PW4eQXkvMylawSut mArHVH6AAxIK+defeEmnQCJ0OccyGCENjRDuWyWMMGoP/ggZpO47rGWmCUOK8xz8 IfGdPeF/9xsKSKWvjpiHyyKa48wuO2bVC+5bISS6IPA2uGneS2DpmjkHU+gHBqpk GNlvEnXZfavZOHejE7/L/Q== =hJ4/ -----END PGP SIGNATURE----- Merge tag 'pull-target-arm-20250711' of https://gitlab.com/pm215/qemu into staging target-arm queue: * New board type max78000fthr * Enable use of CXL on Arm 'virt' board * Some more tidyup of ID register handling * Refactor AT insns and PMU regs into separate source files * Don't enforce NSE,NS check for EL3->EL3 returns * hw/arm/fsl-imx8mp: Wire VIRQ and VFIQ * Allow nested-virtualization with KVM on the 'virt' board * system/qdev: Remove pointless NULL check in qdev_device_add_from_qdict * hw/arm/virt-acpi-build: Don't create ITS id mappings by default * target/arm: Remove unused helper_sme2_luti4_4b # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmhxEcoZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3j5yEACWYnNeqo8Yph6/EJExE6eV # r0tC6FBb5ShPgA6kDxhpOc1lI6uXGh8+D7bL9BePEdz/brCf1QDfs2Z4q/hb5ysX # D0H6VI5Gr1j6MjkFRBo3+vvYz4Yh++XLn5Q9lZv8zaSEdraq/ay2kxnuhRCK+4Ar # +QoGtKrGMJ7UCpfiRlvNnd1UjgORZf10EE/bRImX13sxeDomP3CZhFzAyJyShOP9 # JA7bAd4rYJ4oj8R33y8Yaxjwm4FOndj740B0zwpO8mpjzFiE5zbqsaO+mEgYSflc # OQisCu/KRFpyIR+UqP+4gNaJLfKQW5Y4r61zEaiJWV/c4RdKNnbK1f7MX11fNhOk # k1paF3GIXp6f794Hb14vtsYnKHF2eeNSmRkAomXxLgUSYzLezL+yj7cdYmRJhgYU # thc1PSiEmHYhjRmOaMC9+dkMtvIexWyDNYNFTygoOE5/kTMSazeTFQpFmw+ZuTee # 9pjKsYRZJgTa64IkJy1L34jc2gds48Q20KpQsqZ22KQcjwt4PW4eQXkvMylawSut # mArHVH6AAxIK+defeEmnQCJ0OccyGCENjRDuWyWMMGoP/ggZpO47rGWmCUOK8xz8 # IfGdPeF/9xsKSKWvjpiHyyKa48wuO2bVC+5bISS6IPA2uGneS2DpmjkHU+gHBqpk # GNlvEnXZfavZOHejE7/L/Q== # =hJ4/ # -----END PGP SIGNATURE----- # gpg: Signature made Fri 11 Jul 2025 09:29:46 EDT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20250711' of https://gitlab.com/pm215/qemu: (36 commits) tests/functional: Add a test for the MAX78000 arm machine docs/system: arm: Add max78000 board description target/arm: Remove helper_sme2_luti4_4b hw/arm/virt-acpi-build: Don't create ITS id mappings by default system/qdev: Remove pointless NULL check in qdev_device_add_from_qdict hw/arm/virt: Allow virt extensions with KVM hw/arm/arm_gicv3_kvm: Add a migration blocker with kvm nested virt target/arm: Enable feature ARM_FEATURE_EL2 if EL2 is supported target/arm/kvm: Add helper to detect EL2 when using KVM hw/arm: Allow setting KVM vGIC maintenance IRQ hw/arm/fsl-imx8mp: Wire VIRQ and VFIQ target/arm: Don't enforce NSE,NS check for EL3->EL3 returns target/arm: Split out performance monitor regs to cpregs-pmu.c target/arm: Split out AT insns to tcg/cpregs-at.c target/arm: Drop stub for define_tlb_insn_regs arm/kvm: shorten one overly long line arm/cpu: store clidr into the idregs array arm/cpu: fix trailing ',' for SET_IDREG arm/cpu: store id_aa64afr{0,1} into the idregs array arm/cpu: store id_afr0 into the idregs array ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi
commit
0edc2afe0c
62 changed files with 4300 additions and 2010 deletions
50
include/hw/arm/max78000_soc.h
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50
include/hw/arm/max78000_soc.h
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@ -0,0 +1,50 @@
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/*
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* MAX78000 SOC
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*
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* Copyright (c) 2025 Jackson Donaldson <jcksn@duck.com>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef HW_ARM_MAX78000_SOC_H
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#define HW_ARM_MAX78000_SOC_H
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#include "hw/or-irq.h"
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#include "hw/arm/armv7m.h"
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#include "hw/misc/max78000_aes.h"
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#include "hw/misc/max78000_gcr.h"
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#include "hw/misc/max78000_icc.h"
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#include "hw/char/max78000_uart.h"
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#include "hw/misc/max78000_trng.h"
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#include "qom/object.h"
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#define TYPE_MAX78000_SOC "max78000-soc"
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OBJECT_DECLARE_SIMPLE_TYPE(MAX78000State, MAX78000_SOC)
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#define FLASH_BASE_ADDRESS 0x10000000
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#define FLASH_SIZE (512 * 1024)
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#define SRAM_BASE_ADDRESS 0x20000000
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#define SRAM_SIZE (128 * 1024)
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/* The MAX78k has 2 instruction caches; only icc0 matters, icc1 is for RISC */
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#define MAX78000_NUM_ICC 2
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#define MAX78000_NUM_UART 3
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struct MAX78000State {
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SysBusDevice parent_obj;
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ARMv7MState armv7m;
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MemoryRegion sram;
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MemoryRegion flash;
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Max78000GcrState gcr;
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Max78000IccState icc[MAX78000_NUM_ICC];
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Max78000UartState uart[MAX78000_NUM_UART];
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Max78000TrngState trng;
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Max78000AesState aes;
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Clock *sysclk;
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};
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#endif
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@ -36,6 +36,7 @@
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#include "hw/arm/boot.h"
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#include "hw/arm/bsa.h"
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#include "hw/block/flash.h"
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#include "hw/cxl/cxl.h"
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#include "system/kvm.h"
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#include "hw/intc/arm_gicv3_common.h"
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#include "qom/object.h"
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@ -85,6 +86,7 @@ enum {
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/* indices of IO regions located after the RAM */
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enum {
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VIRT_HIGH_GIC_REDIST2 = VIRT_LOWMEMMAP_LAST,
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VIRT_CXL_HOST,
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VIRT_HIGH_PCIE_ECAM,
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VIRT_HIGH_PCIE_MMIO,
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};
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@ -140,6 +142,7 @@ struct VirtMachineState {
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bool secure;
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bool highmem;
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bool highmem_compact;
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bool highmem_cxl;
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bool highmem_ecam;
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bool highmem_mmio;
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bool highmem_redists;
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@ -174,6 +177,7 @@ struct VirtMachineState {
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char *oem_id;
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char *oem_table_id;
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bool ns_el2_virt_timer_irq;
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CXLState cxl_devices_state;
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};
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#define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM)
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78
include/hw/char/max78000_uart.h
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78
include/hw/char/max78000_uart.h
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@ -0,0 +1,78 @@
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/*
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* MAX78000 UART
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*
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* Copyright (c) 2025 Jackson Donaldson <jcksn@duck.com>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef HW_MAX78000_UART_H
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#define HW_MAX78000_UART_H
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#include "hw/sysbus.h"
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#include "chardev/char-fe.h"
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#include "qemu/fifo8.h"
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#include "qom/object.h"
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#define UART_CTRL 0x0
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#define UART_STATUS 0x4
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#define UART_INT_EN 0x8
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#define UART_INT_FL 0xc
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#define UART_CLKDIV 0x10
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#define UART_OSR 0x14
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#define UART_TXPEEK 0x18
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#define UART_PNR 0x1c
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#define UART_FIFO 0x20
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#define UART_DMA 0x30
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#define UART_WKEN 0x34
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#define UART_WKFL 0x38
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/* CTRL */
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#define UART_CTF_DIS (1 << 7)
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#define UART_FLUSH_TX (1 << 8)
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#define UART_FLUSH_RX (1 << 9)
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#define UART_BCLKEN (1 << 15)
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#define UART_BCLKRDY (1 << 19)
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/* STATUS */
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#define UART_RX_LVL 8
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#define UART_TX_EM (1 << 6)
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#define UART_RX_FULL (1 << 5)
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#define UART_RX_EM (1 << 4)
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/* PNR (Pin Control Register) */
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#define UART_CTS 1
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#define UART_RTS (1 << 1)
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/* INT_EN / INT_FL */
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#define UART_RX_THD (1 << 4)
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#define UART_TX_HE (1 << 6)
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#define UART_RXBUFLEN 0x100
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#define TYPE_MAX78000_UART "max78000-uart"
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OBJECT_DECLARE_SIMPLE_TYPE(Max78000UartState, MAX78000_UART)
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struct Max78000UartState {
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SysBusDevice parent_obj;
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MemoryRegion mmio;
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uint32_t ctrl;
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uint32_t status;
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uint32_t int_en;
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uint32_t int_fl;
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uint32_t clkdiv;
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uint32_t osr;
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uint32_t txpeek;
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uint32_t pnr;
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uint32_t fifo;
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uint32_t dma;
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uint32_t wken;
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uint32_t wkfl;
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Fifo8 rx_fifo;
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CharBackend chr;
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qemu_irq irq;
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};
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#endif /* HW_STM32F2XX_USART_H */
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@ -27,6 +27,8 @@
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typedef struct PXBCXLDev PXBCXLDev;
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typedef struct CXLFixedWindow {
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SysBusDevice parent_obj;
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int index;
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uint64_t size;
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char **targets;
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PXBCXLDev *target_hbs[16];
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@ -37,12 +39,13 @@ typedef struct CXLFixedWindow {
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MemoryRegion mr;
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hwaddr base;
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} CXLFixedWindow;
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#define TYPE_CXL_FMW "cxl-fmw"
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OBJECT_DECLARE_SIMPLE_TYPE(CXLFixedWindow, CXL_FMW)
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typedef struct CXLState {
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bool is_enabled;
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MemoryRegion host_mr;
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unsigned int next_mr_idx;
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GList *fixed_windows;
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CXLFixedMemoryWindowOptionsList *cfmw_list;
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} CXLState;
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@ -14,8 +14,11 @@
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#define CXL_HOST_H
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void cxl_machine_init(Object *obj, CXLState *state);
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void cxl_fmws_link_targets(CXLState *stat, Error **errp);
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void cxl_fmws_link_targets(Error **errp);
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void cxl_hook_up_pxb_registers(PCIBus *bus, CXLState *state, Error **errp);
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hwaddr cxl_fmws_set_memmap(hwaddr base, hwaddr max_addr);
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void cxl_fmws_update_mmio(void);
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GSList *cxl_fmws_get_all_sorted(void);
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extern const MemoryRegionOps cfmws_ops;
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@ -231,6 +231,7 @@ struct GICv3State {
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uint32_t num_cpu;
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uint32_t num_irq;
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uint32_t revision;
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uint32_t maint_irq;
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bool lpi_enable;
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bool nmi_support;
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bool security_extn;
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68
include/hw/misc/max78000_aes.h
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68
include/hw/misc/max78000_aes.h
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/*
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* MAX78000 AES
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*
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* Copyright (c) 2025 Jackson Donaldson <jcksn@duck.com>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef HW_MAX78000_AES_H
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#define HW_MAX78000_AES_H
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#include "hw/sysbus.h"
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#include "crypto/aes.h"
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#include "qom/object.h"
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#define TYPE_MAX78000_AES "max78000-aes"
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OBJECT_DECLARE_SIMPLE_TYPE(Max78000AesState, MAX78000_AES)
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#define CTRL 0
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#define STATUS 4
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#define INTFL 8
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#define INTEN 0xc
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#define FIFO 0x10
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#define KEY_BASE 0x400
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#define KEY_END 0x420
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/* CTRL */
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#define TYPE (1 << 9 | 1 << 8)
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#define KEY_SIZE (1 << 7 | 1 << 6)
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#define OUTPUT_FLUSH (1 << 5)
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#define INPUT_FLUSH (1 << 4)
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#define START (1 << 3)
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#define AES_EN (1 << 0)
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/* STATUS */
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#define OUTPUT_FULL (1 << 4)
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#define OUTPUT_EMPTY (1 << 3)
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#define INPUT_FULL (1 << 2)
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#define INPUT_EMPTY (1 << 1)
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#define BUSY (1 << 0)
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/* INTFL*/
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#define DONE (1 << 0)
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struct Max78000AesState {
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SysBusDevice parent_obj;
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MemoryRegion mmio;
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uint32_t ctrl;
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uint32_t status;
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uint32_t intfl;
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uint32_t inten;
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uint32_t data_index;
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uint8_t data[16];
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uint8_t key[32];
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AES_KEY internal_key;
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uint32_t result_index;
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uint8_t result[16];
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qemu_irq irq;
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};
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#endif
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131
include/hw/misc/max78000_gcr.h
Normal file
131
include/hw/misc/max78000_gcr.h
Normal file
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@ -0,0 +1,131 @@
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/*
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* MAX78000 Global Control Register
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*
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* Copyright (c) 2025 Jackson Donaldson <jcksn@duck.com>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef HW_MAX78000_GCR_H
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#define HW_MAX78000_GCR_H
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#include "hw/sysbus.h"
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#include "qom/object.h"
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#define TYPE_MAX78000_GCR "max78000-gcr"
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OBJECT_DECLARE_SIMPLE_TYPE(Max78000GcrState, MAX78000_GCR)
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#define SYSCTRL 0x0
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#define RST0 0x4
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#define CLKCTRL 0x8
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#define PM 0xc
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#define PCLKDIV 0x18
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#define PCLKDIS0 0x24
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#define MEMCTRL 0x28
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#define MEMZ 0x2c
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#define SYSST 0x40
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#define RST1 0x44
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#define PCKDIS1 0x48
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#define EVENTEN 0x4c
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#define REVISION 0x50
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#define SYSIE 0x54
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#define ECCERR 0x64
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#define ECCED 0x68
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#define ECCIE 0x6c
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#define ECCADDR 0x70
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/* RST0 */
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#define SYSTEM_RESET (1 << 31)
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#define PERIPHERAL_RESET (1 << 30)
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#define SOFT_RESET (1 << 29)
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#define UART2_RESET (1 << 28)
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#define ADC_RESET (1 << 26)
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#define CNN_RESET (1 << 25)
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#define TRNG_RESET (1 << 24)
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#define RTC_RESET (1 << 17)
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#define I2C0_RESET (1 << 16)
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#define SPI1_RESET (1 << 13)
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#define UART1_RESET (1 << 12)
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#define UART0_RESET (1 << 11)
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#define TMR3_RESET (1 << 8)
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#define TMR2_RESET (1 << 7)
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#define TMR1_RESET (1 << 6)
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#define TMR0_RESET (1 << 5)
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#define GPIO1_RESET (1 << 3)
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#define GPIO0_RESET (1 << 2)
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#define WDT0_RESET (1 << 1)
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#define DMA_RESET (1 << 0)
|
||||
|
||||
/* CLKCTRL */
|
||||
#define SYSCLK_RDY (1 << 13)
|
||||
|
||||
/* MEMZ */
|
||||
#define ram0 (1 << 0)
|
||||
#define ram1 (1 << 1)
|
||||
#define ram2 (1 << 2)
|
||||
#define ram3 (1 << 3)
|
||||
|
||||
/* RST1 */
|
||||
#define CPU1_RESET (1 << 31)
|
||||
|
||||
#define SIMO_RESET (1 << 25)
|
||||
#define DVS_RESET (1 << 24)
|
||||
|
||||
#define I2C2_RESET (1 << 20)
|
||||
#define I2S_RESET (1 << 19)
|
||||
|
||||
#define SMPHR_RESET (1 << 16)
|
||||
|
||||
#define SPI0_RESET (1 << 11)
|
||||
#define AES_RESET (1 << 10)
|
||||
#define CRC_RESET (1 << 9)
|
||||
|
||||
#define PT_RESET (1 << 1)
|
||||
#define I2C1_RESET (1 << 0)
|
||||
|
||||
|
||||
#define SYSRAM0_START 0x20000000
|
||||
#define SYSRAM1_START 0x20008000
|
||||
#define SYSRAM2_START 0x20010000
|
||||
#define SYSRAM3_START 0x2001C000
|
||||
|
||||
struct Max78000GcrState {
|
||||
SysBusDevice parent_obj;
|
||||
|
||||
MemoryRegion mmio;
|
||||
|
||||
uint32_t sysctrl;
|
||||
uint32_t rst0;
|
||||
uint32_t clkctrl;
|
||||
uint32_t pm;
|
||||
uint32_t pclkdiv;
|
||||
uint32_t pclkdis0;
|
||||
uint32_t memctrl;
|
||||
uint32_t memz;
|
||||
uint32_t sysst;
|
||||
uint32_t rst1;
|
||||
uint32_t pckdis1;
|
||||
uint32_t eventen;
|
||||
uint32_t revision;
|
||||
uint32_t sysie;
|
||||
uint32_t eccerr;
|
||||
uint32_t ecced;
|
||||
uint32_t eccie;
|
||||
uint32_t eccaddr;
|
||||
|
||||
MemoryRegion *sram;
|
||||
AddressSpace sram_as;
|
||||
|
||||
DeviceState *uart0;
|
||||
DeviceState *uart1;
|
||||
DeviceState *uart2;
|
||||
DeviceState *trng;
|
||||
DeviceState *aes;
|
||||
|
||||
};
|
||||
|
||||
#endif
|
||||
33
include/hw/misc/max78000_icc.h
Normal file
33
include/hw/misc/max78000_icc.h
Normal file
|
|
@ -0,0 +1,33 @@
|
|||
/*
|
||||
* MAX78000 Instruction Cache
|
||||
*
|
||||
* Copyright (c) 2025 Jackson Donaldson <jcksn@duck.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0-or-later
|
||||
*/
|
||||
|
||||
#ifndef HW_MAX78000_ICC_H
|
||||
#define HW_MAX78000_ICC_H
|
||||
|
||||
#include "hw/sysbus.h"
|
||||
#include "qom/object.h"
|
||||
|
||||
#define TYPE_MAX78000_ICC "max78000-icc"
|
||||
OBJECT_DECLARE_SIMPLE_TYPE(Max78000IccState, MAX78000_ICC)
|
||||
|
||||
#define ICC_INFO 0x0
|
||||
#define ICC_SZ 0x4
|
||||
#define ICC_CTRL 0x100
|
||||
#define ICC_INVALIDATE 0x700
|
||||
|
||||
struct Max78000IccState {
|
||||
SysBusDevice parent_obj;
|
||||
|
||||
MemoryRegion mmio;
|
||||
|
||||
uint32_t info;
|
||||
uint32_t sz;
|
||||
uint32_t ctrl;
|
||||
};
|
||||
|
||||
#endif
|
||||
35
include/hw/misc/max78000_trng.h
Normal file
35
include/hw/misc/max78000_trng.h
Normal file
|
|
@ -0,0 +1,35 @@
|
|||
/*
|
||||
* MAX78000 True Random Number Generator
|
||||
*
|
||||
* Copyright (c) 2025 Jackson Donaldson <jcksn@duck.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0-or-later
|
||||
*/
|
||||
#ifndef HW_MAX78000_TRNG_H
|
||||
#define HW_MAX78000_TRNG_H
|
||||
|
||||
#include "hw/sysbus.h"
|
||||
#include "qom/object.h"
|
||||
|
||||
#define TYPE_MAX78000_TRNG "max78000-trng"
|
||||
OBJECT_DECLARE_SIMPLE_TYPE(Max78000TrngState, MAX78000_TRNG)
|
||||
|
||||
#define CTRL 0
|
||||
#define STATUS 4
|
||||
#define DATA 8
|
||||
|
||||
#define RND_IE (1 << 1)
|
||||
|
||||
struct Max78000TrngState {
|
||||
SysBusDevice parent_obj;
|
||||
|
||||
MemoryRegion mmio;
|
||||
|
||||
uint32_t ctrl;
|
||||
uint32_t status;
|
||||
uint32_t data;
|
||||
|
||||
qemu_irq irq;
|
||||
};
|
||||
|
||||
#endif
|
||||
Loading…
Add table
Add a link
Reference in a new issue