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target/hexagon: s/pkt_has_store/pkt_has_scalar_store

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To remove any confusion with HVX or other potential store instructions,
we'll qualify this context var with "scalar".

Reviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com>
Reviewed-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
This commit is contained in:
Brian Cain 2025-04-07 12:27:04 -07:00
parent 0c8a4e8434
commit 1118972ef5
9 changed files with 21 additions and 19 deletions
Download patch file Download diff file Expand all files Collapse all files

4
target/hexagon/decode.c
View file

@ -236,9 +236,9 @@ static void decode_set_insn_attr_fields(Packet *pkt)
if (GET_ATTRIB(opcode, A_SCALAR_STORE) &&
!GET_ATTRIB(opcode, A_MEMSIZE_0B)) {
if (pkt->insn[i].slot == 0) {
pkt->pkt_has_store_s0 = true;
pkt->pkt_has_scalar_store_s0 = true;
} else {
pkt->pkt_has_store_s1 = true;
pkt->pkt_has_scalar_store_s1 = true;
}
}
}

2
target/hexagon/gen_helper_funcs.py
View file

@ -69,7 +69,7 @@ def gen_helper_function(f, tag, tagregs, tagimms):
if hex_common.need_slot(tag):
if "A_LOAD" in hex_common.attribdict[tag]:
f.write(hex_common.code_fmt(f"""\
bool pkt_has_store_s1 = slotval & 0x1;
bool pkt_has_scalar_store_s1 = slotval & 0x1;
"""))
f.write(hex_common.code_fmt(f"""\
uint32_t slot = slotval >> 1;

3
target/hexagon/genptr.c
View file

@ -395,7 +395,8 @@ static inline void gen_store_conditional8(DisasContext *ctx,
#ifndef CONFIG_HEXAGON_IDEF_PARSER
static TCGv gen_slotval(DisasContext *ctx)
{
int slotval = (ctx->pkt->pkt_has_store_s1 & 1) | (ctx->insn->slot << 1);
int slotval =
(ctx->pkt->pkt_has_scalar_store_s1 & 1) | (ctx->insn->slot << 1);
return tcg_constant_tl(slotval);
}
#endif

2
target/hexagon/idef-parser/README.rst
View file

@ -637,7 +637,7 @@ tinycode for the Hexagon ``add`` instruction
::
---- 00021094
mov_i32 pkt_has_store_s1,$0x0
mov_i32 pkt_has_scalar_store_s1,$0x0
add_i32 tmp0,r2,r2
mov_i32 loc2,tmp0
mov_i32 new_r1,loc2

4
target/hexagon/idef-parser/parser-helpers.c
View file

@ -1725,7 +1725,7 @@ void gen_cancel(Context *c, YYLTYPE *locp)
void gen_load_cancel(Context *c, YYLTYPE *locp)
{
OUT(c, locp, "if (insn->slot == 0 && pkt->pkt_has_store_s1) {\n");
OUT(c, locp, "if (insn->slot == 0 && pkt->pkt_has_scalar_store_s1) {\n");
OUT(c, locp, "ctx->s1_store_processed = false;\n");
OUT(c, locp, "process_store(ctx, 1);\n");
OUT(c, locp, "}\n");
@ -1750,7 +1750,7 @@ void gen_load(Context *c, YYLTYPE *locp, HexValue *width,
/* Lookup the effective address EA */
find_variable(c, locp, ea, ea);
OUT(c, locp, "if (insn->slot == 0 && pkt->pkt_has_store_s1) {\n");
OUT(c, locp, "if (insn->slot == 0 && pkt->pkt_has_scalar_store_s1) {\n");
OUT(c, locp, "probe_noshuf_load(", ea, ", ", width, ", ctx->mem_idx);\n");
OUT(c, locp, "process_store(ctx, 1);\n");
OUT(c, locp, "}\n");

4
target/hexagon/insn.h
View file

@ -66,8 +66,8 @@ struct Packet {
bool pkt_has_dczeroa;
bool pkt_has_store_s0;
bool pkt_has_store_s1;
bool pkt_has_scalar_store_s0;
bool pkt_has_scalar_store_s1;
bool pkt_has_hvx;
Insn *vhist_insn;

8
target/hexagon/macros.h
View file

@ -83,7 +83,7 @@
*/
#define CHECK_NOSHUF(VA, SIZE) \
do { \
if (insn->slot == 0 && ctx->pkt->pkt_has_store_s1) { \
if (insn->slot == 0 && ctx->pkt->pkt_has_scalar_store_s1) { \
probe_noshuf_load(VA, SIZE, ctx->mem_idx); \
process_store(ctx, 1); \
} \
@ -94,11 +94,11 @@
TCGLabel *noshuf_label = gen_new_label(); \
tcg_gen_brcondi_tl(TCG_COND_EQ, PRED, 0, noshuf_label); \
GET_EA; \
if (insn->slot == 0 && ctx->pkt->pkt_has_store_s1) { \
if (insn->slot == 0 && ctx->pkt->pkt_has_scalar_store_s1) { \
probe_noshuf_load(EA, SIZE, ctx->mem_idx); \
} \
gen_set_label(noshuf_label); \
if (insn->slot == 0 && ctx->pkt->pkt_has_store_s1) { \
if (insn->slot == 0 && ctx->pkt->pkt_has_scalar_store_s1) { \
process_store(ctx, 1); \
} \
} while (0)
@ -525,7 +525,7 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift)
#define fLOAD(NUM, SIZE, SIGN, EA, DST) \
do { \
check_noshuf(env, pkt_has_store_s1, slot, EA, SIZE, GETPC()); \
check_noshuf(env, pkt_has_scalar_store_s1, slot, EA, SIZE, GETPC()); \
DST = (size##SIZE##SIGN##_t)MEM_LOAD##SIZE(env, EA, GETPC()); \
} while (0)
#endif

4
target/hexagon/op_helper.c
View file

@ -463,11 +463,11 @@ void HELPER(probe_pkt_scalar_hvx_stores)(CPUHexagonState *env, int mask)
* If the load is in slot 0 and there is a store in slot1 (that
* wasn't cancelled), we have to do the store first.
*/
static void check_noshuf(CPUHexagonState *env, bool pkt_has_store_s1,
static void check_noshuf(CPUHexagonState *env, bool pkt_has_scalar_store_s1,
uint32_t slot, target_ulong vaddr, int size,
uintptr_t ra)
{
if (slot == 0 && pkt_has_store_s1 &&
if (slot == 0 && pkt_has_scalar_store_s1 &&
((env->slot_cancelled & (1 << 1)) == 0)) {
probe_read(env, vaddr, size, MMU_USER_IDX, ra);
commit_store(env, 1, ra);

9
target/hexagon/translate.c
View file

@ -693,11 +693,11 @@ static void process_store_log(DisasContext *ctx)
* the memory accesses overlap.
*/
Packet *pkt = ctx->pkt;
if (pkt->pkt_has_store_s1) {
if (pkt->pkt_has_scalar_store_s1) {
g_assert(!pkt->pkt_has_dczeroa);
process_store(ctx, 1);
}
if (pkt->pkt_has_store_s0) {
if (pkt->pkt_has_scalar_store_s0) {
g_assert(!pkt->pkt_has_dczeroa);
process_store(ctx, 0);
}
@ -822,8 +822,9 @@ static void gen_commit_packet(DisasContext *ctx)
* involved in committing the packet.
*/
Packet *pkt = ctx->pkt;
bool has_store_s0 = pkt->pkt_has_store_s0;
bool has_store_s1 = (pkt->pkt_has_store_s1 && !ctx->s1_store_processed);
bool has_store_s0 = pkt->pkt_has_scalar_store_s0;
bool has_store_s1 =
(pkt->pkt_has_scalar_store_s1 && !ctx->s1_store_processed);
bool has_hvx_store = pkt_has_hvx_store(pkt);
if (pkt->pkt_has_dczeroa) {
/*