* i386: fix migration issues in 10.1
* target/i386/mshv: new accelerator * rust: use glib-sys-rs * rust: fixes for docker tests -----BEGIN PGP SIGNATURE----- iQFIBAABCgAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmjnaOwUHHBib256aW5p QHJlZGhhdC5jb20ACgkQv/vSX3jHroNsFQf/WXKxZLLnItHwDz3UdwjzewPWpz5N fpS0E4C03J8pACDgyfl7PQl47P7NlJ08Ig2Lc5l3Z9KiAKgh0orR7Cqd0BY5f9lo uk4FgXfXpQyApywAlctadrTfcH8sRv2tMaP6EJ9coLtJtHW9RUGFPaZeMsqrjpAl TpwAXPYNDDvvy1ih1LPh5DzOPDXE4pin2tDa94gJei56gY95auK4zppoNYLdB3kR GOyR4QK43/yhuxPHOmQCZOE3HK2XrKgMZHWIjAovjZjZFiJs49FaHBOpRfFpsUlG PB3UbIMtu69VY20LqbbyInPnyATRQzqIGnDGTErP6lfCGTKTy2ulQYWvHA== =KM5O -----END PGP SIGNATURE----- Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging * i386: fix migration issues in 10.1 * target/i386/mshv: new accelerator * rust: use glib-sys-rs * rust: fixes for docker tests # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCgAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmjnaOwUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroNsFQf/WXKxZLLnItHwDz3UdwjzewPWpz5N # fpS0E4C03J8pACDgyfl7PQl47P7NlJ08Ig2Lc5l3Z9KiAKgh0orR7Cqd0BY5f9lo # uk4FgXfXpQyApywAlctadrTfcH8sRv2tMaP6EJ9coLtJtHW9RUGFPaZeMsqrjpAl # TpwAXPYNDDvvy1ih1LPh5DzOPDXE4pin2tDa94gJei56gY95auK4zppoNYLdB3kR # GOyR4QK43/yhuxPHOmQCZOE3HK2XrKgMZHWIjAovjZjZFiJs49FaHBOpRfFpsUlG # PB3UbIMtu69VY20LqbbyInPnyATRQzqIGnDGTErP6lfCGTKTy2ulQYWvHA== # =KM5O # -----END PGP SIGNATURE----- # gpg: Signature made Thu 09 Oct 2025 12:49:00 AM PDT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [unknown] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [unknown] # gpg: WARNING: The key's User ID is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (35 commits) rust: fix path to rust_root_crate.sh tests/docker: make --enable-rust overridable with EXTRA_CONFIGURE_OPTS MAINTAINERS: Add maintainers for mshv accelerator docs: Add mshv to documentation target/i386/mshv: Use preallocated page for hvcall qapi/accel: Allow to query mshv capabilities accel/mshv: Handle overlapping mem mappings target/i386/mshv: Implement mshv_vcpu_run() target/i386/mshv: Write MSRs to the hypervisor target/i386/mshv: Integrate x86 instruction decoder/emulator target/i386/mshv: Register MSRs with MSHV target/i386/mshv: Register CPUID entries with MSHV target/i386/mshv: Set local interrupt controller state target/i386/mshv: Implement mshv_arch_put_registers() target/i386/mshv: Implement mshv_get_special_regs() target/i386/mshv: Implement mshv_get_standard_regs() target/i386/mshv: Implement mshv_store_regs() target/i386/mshv: Add CPU create and remove logic accel/mshv: Add vCPU signal handling accel/mshv: Add vCPU creation and execution loop ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
commit
1188b07e60
87 changed files with 6617 additions and 79 deletions
37
include/system/accel-irq.h
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37
include/system/accel-irq.h
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@ -0,0 +1,37 @@
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/*
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* Accelerated irqchip abstraction
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*
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* Copyright Microsoft, Corp. 2025
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*
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* Authors: Ziqiao Zhou <ziqiaozhou@microsoft.com>
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* Magnus Kulke <magnuskulke@microsoft.com>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef SYSTEM_ACCEL_IRQ_H
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#define SYSTEM_ACCEL_IRQ_H
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#include "hw/pci/msi.h"
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#include "qemu/osdep.h"
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#include "system/kvm.h"
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#include "system/mshv.h"
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static inline bool accel_msi_via_irqfd_enabled(void)
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{
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return mshv_msi_via_irqfd_enabled() || kvm_msi_via_irqfd_enabled();
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}
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static inline bool accel_irqchip_is_split(void)
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{
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return mshv_msi_via_irqfd_enabled() || kvm_irqchip_is_split();
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}
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int accel_irqchip_add_msi_route(KVMRouteChange *c, int vector, PCIDevice *dev);
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int accel_irqchip_update_msi_route(int vector, MSIMessage msg, PCIDevice *dev);
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void accel_irqchip_commit_route_changes(KVMRouteChange *c);
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void accel_irqchip_commit_routes(void);
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void accel_irqchip_release_virq(int virq);
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int accel_irqchip_add_irqfd_notifier_gsi(EventNotifier *n, EventNotifier *rn,
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int virq);
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int accel_irqchip_remove_irqfd_notifier_gsi(EventNotifier *n, int virq);
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#endif
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@ -14,6 +14,7 @@
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#include "hw/core/cpu.h"
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#include "system/kvm.h"
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#include "system/hvf.h"
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#include "system/mshv.h"
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#include "system/whpx.h"
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#include "system/nvmm.h"
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64
include/system/mshv.h
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64
include/system/mshv.h
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@ -0,0 +1,64 @@
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/*
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* QEMU MSHV support
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*
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* Copyright Microsoft, Corp. 2025
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*
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* Authors: Ziqiao Zhou <ziqiaozhou@microsoft.com>
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* Magnus Kulke <magnuskulke@microsoft.com>
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* Jinank Jain <jinankjain@microsoft.com>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*
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*/
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#ifndef QEMU_MSHV_H
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#define QEMU_MSHV_H
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#include "qemu/osdep.h"
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#include "qemu/accel.h"
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#include "hw/hyperv/hyperv-proto.h"
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#include "hw/hyperv/hvhdk.h"
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#include "hw/hyperv/hvgdk_mini.h"
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#include "qapi/qapi-types-common.h"
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#include "system/memory.h"
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#include "accel/accel-ops.h"
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#ifdef COMPILING_PER_TARGET
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#ifdef CONFIG_MSHV
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#include <linux/mshv.h>
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#define CONFIG_MSHV_IS_POSSIBLE
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#endif
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#else
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#define CONFIG_MSHV_IS_POSSIBLE
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#endif
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#define MSHV_MAX_MSI_ROUTES 4096
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#define MSHV_PAGE_SHIFT 12
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#ifdef CONFIG_MSHV_IS_POSSIBLE
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extern bool mshv_allowed;
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#define mshv_enabled() (mshv_allowed)
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#define mshv_msi_via_irqfd_enabled() mshv_enabled()
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#else /* CONFIG_MSHV_IS_POSSIBLE */
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#define mshv_enabled() false
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#define mshv_msi_via_irqfd_enabled() mshv_enabled()
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#endif
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typedef struct MshvState MshvState;
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extern MshvState *mshv_state;
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/* interrupt */
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int mshv_request_interrupt(MshvState *mshv_state, uint32_t interrupt_type, uint32_t vector,
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uint32_t vp_index, bool logical_destination_mode,
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bool level_triggered);
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int mshv_irqchip_add_msi_route(int vector, PCIDevice *dev);
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int mshv_irqchip_update_msi_route(int virq, MSIMessage msg, PCIDevice *dev);
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void mshv_irqchip_commit_routes(void);
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void mshv_irqchip_release_virq(int virq);
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int mshv_irqchip_add_irqfd_notifier_gsi(const EventNotifier *n,
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const EventNotifier *rn, int virq);
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int mshv_irqchip_remove_irqfd_notifier_gsi(const EventNotifier *n, int virq);
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#endif
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155
include/system/mshv_int.h
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155
include/system/mshv_int.h
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@ -0,0 +1,155 @@
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/*
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* QEMU MSHV support
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*
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* Copyright Microsoft, Corp. 2025
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*
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* Authors: Ziqiao Zhou <ziqiaozhou@microsoft.com>
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* Magnus Kulke <magnuskulke@microsoft.com>
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* Jinank Jain <jinankjain@microsoft.com>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*
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*/
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#ifndef QEMU_MSHV_INT_H
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#define QEMU_MSHV_INT_H
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#define MSHV_MSR_ENTRIES_COUNT 64
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#define MSHV_MAX_MEM_SLOTS 32
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typedef struct hyperv_message hv_message;
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typedef struct MshvHvCallArgs {
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void *base;
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void *input_page;
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void *output_page;
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} MshvHvCallArgs;
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struct AccelCPUState {
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int cpufd;
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bool dirty;
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MshvHvCallArgs hvcall_args;
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};
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typedef struct MshvMemoryListener {
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MemoryListener listener;
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int as_id;
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} MshvMemoryListener;
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typedef struct MshvAddressSpace {
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MshvMemoryListener *ml;
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AddressSpace *as;
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} MshvAddressSpace;
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typedef struct MshvMemorySlotManager {
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size_t n_slots;
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GList *slots;
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QemuMutex mutex;
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} MshvMemorySlotManager;
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struct MshvState {
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AccelState parent_obj;
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int vm;
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MshvMemoryListener memory_listener;
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/* number of listeners */
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int nr_as;
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MshvAddressSpace *as;
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int fd;
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MshvMemorySlotManager msm;
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};
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typedef struct MshvMsiControl {
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bool updated;
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GHashTable *gsi_routes;
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} MshvMsiControl;
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#define mshv_vcpufd(cpu) (cpu->accel->cpufd)
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/* cpu */
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typedef struct MshvFPU {
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uint8_t fpr[8][16];
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uint16_t fcw;
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uint16_t fsw;
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uint8_t ftwx;
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uint8_t pad1;
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uint16_t last_opcode;
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uint64_t last_ip;
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uint64_t last_dp;
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uint8_t xmm[16][16];
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uint32_t mxcsr;
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uint32_t pad2;
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} MshvFPU;
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typedef enum MshvVmExit {
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MshvVmExitIgnore = 0,
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MshvVmExitShutdown = 1,
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MshvVmExitSpecial = 2,
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} MshvVmExit;
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typedef enum MshvRemapResult {
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MshvRemapOk = 0,
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MshvRemapNoMapping = 1,
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MshvRemapNoOverlap = 2,
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} MshvRemapResult;
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void mshv_init_mmio_emu(void);
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int mshv_create_vcpu(int vm_fd, uint8_t vp_index, int *cpu_fd);
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void mshv_remove_vcpu(int vm_fd, int cpu_fd);
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int mshv_configure_vcpu(const CPUState *cpu, const MshvFPU *fpu, uint64_t xcr0);
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int mshv_get_standard_regs(CPUState *cpu);
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int mshv_get_special_regs(CPUState *cpu);
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int mshv_run_vcpu(int vm_fd, CPUState *cpu, hv_message *msg, MshvVmExit *exit);
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int mshv_load_regs(CPUState *cpu);
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int mshv_store_regs(CPUState *cpu);
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int mshv_set_generic_regs(const CPUState *cpu, const hv_register_assoc *assocs,
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size_t n_regs);
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int mshv_arch_put_registers(const CPUState *cpu);
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void mshv_arch_init_vcpu(CPUState *cpu);
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void mshv_arch_destroy_vcpu(CPUState *cpu);
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void mshv_arch_amend_proc_features(
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union hv_partition_synthetic_processor_features *features);
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int mshv_arch_post_init_vm(int vm_fd);
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#if defined COMPILING_PER_TARGET && defined CONFIG_MSHV_IS_POSSIBLE
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int mshv_hvcall(int fd, const struct mshv_root_hvcall *args);
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#endif
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/* memory */
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typedef struct MshvMemorySlot {
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uint64_t guest_phys_addr;
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uint64_t memory_size;
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uint64_t userspace_addr;
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bool readonly;
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bool mapped;
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} MshvMemorySlot;
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MshvRemapResult mshv_remap_overlap_region(int vm_fd, uint64_t gpa);
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int mshv_guest_mem_read(uint64_t gpa, uint8_t *data, uintptr_t size,
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bool is_secure_mode, bool instruction_fetch);
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int mshv_guest_mem_write(uint64_t gpa, const uint8_t *data, uintptr_t size,
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bool is_secure_mode);
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void mshv_set_phys_mem(MshvMemoryListener *mml, MemoryRegionSection *section,
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bool add);
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void mshv_init_memory_slot_manager(MshvState *mshv_state);
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/* msr */
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typedef struct MshvMsrEntry {
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uint32_t index;
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uint32_t reserved;
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uint64_t data;
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} MshvMsrEntry;
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typedef struct MshvMsrEntries {
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MshvMsrEntry entries[MSHV_MSR_ENTRIES_COUNT];
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uint32_t nmsrs;
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} MshvMsrEntries;
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int mshv_configure_msr(const CPUState *cpu, const MshvMsrEntry *msrs,
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size_t n_msrs);
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/* interrupt */
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void mshv_init_msicontrol(void);
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int mshv_reserve_ioapic_msi_routes(int vm_fd);
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#endif
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