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target/riscv: Conceal MO_TE within gen_inc()

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All callers of gen_inc() set the MO_TE flag. Set it once in
the callee.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20251010155045.78220-5-philmd@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Philippe Mathieu-Daudé 2025-10-10 17:50:35 +02:00 • committed by Alistair Francis
parent cb2725db0c
commit 133080735c
1 changed files with 18 additions and 16 deletions
Download patch file Download diff file Expand all files Collapse all files

34
target/riscv/insn_trans/trans_xthead.c.inc
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@ -568,6 +568,7 @@ static bool gen_load_inc(DisasContext *ctx, arg_th_meminc *a, MemOp memop,
TCGv rd = dest_gpr(ctx, a->rd);
TCGv rs1 = get_gpr(ctx, a->rs1, EXT_NONE);
memop |= MO_TE;
tcg_gen_qemu_ld_tl(rd, addr, ctx->mem_idx, memop);
tcg_gen_addi_tl(rs1, rs1, imm);
gen_set_gpr(ctx, a->rd, rd);
@ -588,6 +589,7 @@ static bool gen_store_inc(DisasContext *ctx, arg_th_meminc *a, MemOp memop,
TCGv data = get_gpr(ctx, a->rd, EXT_NONE);
TCGv rs1 = get_gpr(ctx, a->rs1, EXT_NONE);
memop |= MO_TE;
tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop);
tcg_gen_addi_tl(rs1, rs1, imm);
gen_set_gpr(ctx, a->rs1, rs1);
@ -598,64 +600,64 @@ static bool trans_th_ldia(DisasContext *ctx, arg_th_meminc *a)
{
REQUIRE_XTHEADMEMIDX(ctx);
REQUIRE_64BIT(ctx);
return gen_load_inc(ctx, a, MO_TE | MO_SQ, false);
return gen_load_inc(ctx, a, MO_SQ, false);
}
static bool trans_th_ldib(DisasContext *ctx, arg_th_meminc *a)
{
REQUIRE_XTHEADMEMIDX(ctx);
REQUIRE_64BIT(ctx);
return gen_load_inc(ctx, a, MO_TE | MO_SQ, true);
return gen_load_inc(ctx, a, MO_SQ, true);
}
static bool trans_th_lwia(DisasContext *ctx, arg_th_meminc *a)
{
REQUIRE_XTHEADMEMIDX(ctx);
return gen_load_inc(ctx, a, MO_TE | MO_SL, false);
return gen_load_inc(ctx, a, MO_SL, false);
}
static bool trans_th_lwib(DisasContext *ctx, arg_th_meminc *a)
{
REQUIRE_XTHEADMEMIDX(ctx);
return gen_load_inc(ctx, a, MO_TE | MO_SL, true);
return gen_load_inc(ctx, a, MO_SL, true);
}
static bool trans_th_lwuia(DisasContext *ctx, arg_th_meminc *a)
{
REQUIRE_XTHEADMEMIDX(ctx);
REQUIRE_64BIT(ctx);
return gen_load_inc(ctx, a, MO_TE | MO_UL, false);
return gen_load_inc(ctx, a, MO_UL, false);
}
static bool trans_th_lwuib(DisasContext *ctx, arg_th_meminc *a)
{
REQUIRE_XTHEADMEMIDX(ctx);
REQUIRE_64BIT(ctx);
return gen_load_inc(ctx, a, MO_TE | MO_UL, true);
return gen_load_inc(ctx, a, MO_UL, true);
}
static bool trans_th_lhia(DisasContext *ctx, arg_th_meminc *a)
{
REQUIRE_XTHEADMEMIDX(ctx);
return gen_load_inc(ctx, a, MO_TE | MO_SW, false);
return gen_load_inc(ctx, a, MO_SW, false);
}
static bool trans_th_lhib(DisasContext *ctx, arg_th_meminc *a)
{
REQUIRE_XTHEADMEMIDX(ctx);
return gen_load_inc(ctx, a, MO_TE | MO_SW, true);
return gen_load_inc(ctx, a, MO_SW, true);
}
static bool trans_th_lhuia(DisasContext *ctx, arg_th_meminc *a)
{
REQUIRE_XTHEADMEMIDX(ctx);
return gen_load_inc(ctx, a, MO_TE | MO_UW, false);
return gen_load_inc(ctx, a, MO_UW, false);
}
static bool trans_th_lhuib(DisasContext *ctx, arg_th_meminc *a)
{
REQUIRE_XTHEADMEMIDX(ctx);
return gen_load_inc(ctx, a, MO_TE | MO_UW, true);
return gen_load_inc(ctx, a, MO_UW, true);
}
static bool trans_th_lbia(DisasContext *ctx, arg_th_meminc *a)
@ -686,38 +688,38 @@ static bool trans_th_sdia(DisasContext *ctx, arg_th_meminc *a)
{
REQUIRE_XTHEADMEMIDX(ctx);
REQUIRE_64BIT(ctx);
return gen_store_inc(ctx, a, MO_TE | MO_SQ, false);
return gen_store_inc(ctx, a, MO_SQ, false);
}
static bool trans_th_sdib(DisasContext *ctx, arg_th_meminc *a)
{
REQUIRE_XTHEADMEMIDX(ctx);
REQUIRE_64BIT(ctx);
return gen_store_inc(ctx, a, MO_TE | MO_SQ, true);
return gen_store_inc(ctx, a, MO_SQ, true);
}
static bool trans_th_swia(DisasContext *ctx, arg_th_meminc *a)
{
REQUIRE_XTHEADMEMIDX(ctx);
return gen_store_inc(ctx, a, MO_TE | MO_SL, false);
return gen_store_inc(ctx, a, MO_SL, false);
}
static bool trans_th_swib(DisasContext *ctx, arg_th_meminc *a)
{
REQUIRE_XTHEADMEMIDX(ctx);
return gen_store_inc(ctx, a, MO_TE | MO_SL, true);
return gen_store_inc(ctx, a, MO_SL, true);
}
static bool trans_th_shia(DisasContext *ctx, arg_th_meminc *a)
{
REQUIRE_XTHEADMEMIDX(ctx);
return gen_store_inc(ctx, a, MO_TE | MO_SW, false);
return gen_store_inc(ctx, a, MO_SW, false);
}
static bool trans_th_shib(DisasContext *ctx, arg_th_meminc *a)
{
REQUIRE_XTHEADMEMIDX(ctx);
return gen_store_inc(ctx, a, MO_TE | MO_SW, true);
return gen_store_inc(ctx, a, MO_SW, true);
}
static bool trans_th_sbia(DisasContext *ctx, arg_th_meminc *a)