From 146214796cbd5a12b0cc3d0acae374292bd64c6d Mon Sep 17 00:00:00 2001 From: Jamin Lin Date: Tue, 3 Feb 2026 10:08:46 +0800 Subject: [PATCH] hw/arm/aspeed_ast27x0: Fix EHCI3/4 IRQ routing to GIC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit EHCI3 and EHCI4 were missing entries in aspeed_soc_ast2700a1_irqmap, so their source IRQs were never routed through the INTC OR-gates. As a result, EHCI3/4 interrupts were not propagated to the GIC, causing incorrect interrupt behavior for these controllers. Add EHCI3 and EHCI4 to the IRQ map and route them to the same INTC group as other shared peripherals, ensuring their interrupts are properly connected to the GIC. Signed-off-by: Jamin Lin Fixes: ba27ba302a264117c8b8427f944ced1bed17c438 ("hw/arm: ast27x0: Wire up EHCI controllers") Reviewed-by: Cédric Le Goater Link: https://lore.kernel.org/qemu-devel/20260203020855.1642884-2-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater (cherry picked from commit 7d64f04863ed23f6a142fb8f47c5a470c0e081f9) Signed-off-by: Michael Tokarev --- hw/arm/aspeed_ast27x0.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 95f155fcf1..ff86020064 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -193,6 +193,8 @@ static const int aspeed_soc_ast2700a1_irqmap[] = { [ASPEED_DEV_ETH1] = 196, [ASPEED_DEV_ETH2] = 196, [ASPEED_DEV_ETH3] = 196, + [ASPEED_DEV_EHCI3] = 196, + [ASPEED_DEV_EHCI4] = 196, [ASPEED_DEV_PECI] = 197, [ASPEED_DEV_SDHCI] = 197, };