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hw/arm/aspeed: Remove AspeedSoCState dependency from aspeed_soc_uart_realize() API

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Refactor aspeed_soc_uart_realize() to take MemoryRegion *, SerialMM *,
and MMIO base addr instead of AspeedSoCState *, decoupling the helper
from SoC state and making it reusable per-UART.

The helper now realizes a single UART instance and maps its MMIO.
IRQ wiring and iteration over all UARTs are moved to callers.

Update call sites in AST1030, AST2400, AST2600, AST27x0 SSP/TSP, and
AST2700 to loop over UARTs, call the new helper, and connect IRQ via
aspeed_soc_get_irq().

This simplifies the UART realize path and reduces cross-module coupling.

No functional change.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20251013054334.955331-8-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
This commit is contained in:
Jamin Lin 2025-10-13 13:43:19 +08:00 • committed by Cédric Le Goater
parent 68f915b91c
commit 15f26071bf
8 changed files with 60 additions and 31 deletions
Download patch file Download diff file Expand all files Collapse all files

10
hw/arm/aspeed_ast10x0.c
View file

@ -192,6 +192,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
DeviceState *armv7m;
Error *err = NULL;
int uart;
int i;
g_autofree char *sram_name = NULL;
@ -316,8 +317,13 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
/* UART */
if (!aspeed_soc_uart_realize(s, errp)) {
return;
for (i = 0, uart = sc->uarts_base; i < sc->uarts_num; i++, uart++) {
if (!aspeed_soc_uart_realize(s->memory, &s->uart[i],
sc->memmap[uart], errp)) {
return;
}
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
aspeed_soc_get_irq(s, uart));
}
/* Timer */

10
hw/arm/aspeed_ast2400.c
View file

@ -251,6 +251,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
AspeedSoCState *s = ASPEED_SOC(dev);
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
g_autofree char *sram_name = NULL;
int uart;
/* Default boot region (SPI memory or ROMs) */
memory_region_init(&s->spi_boot_container, OBJECT(s),
@ -337,8 +338,13 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
aspeed_soc_get_irq(s, ASPEED_DEV_ADC));
/* UART */
if (!aspeed_soc_uart_realize(s, errp)) {
return;
for (i = 0, uart = sc->uarts_base; i < sc->uarts_num; i++, uart++) {
if (!aspeed_soc_uart_realize(s->memory, &s->uart[i],
sc->memmap[uart], errp)) {
return;
}
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
aspeed_soc_get_irq(s, uart));
}
/* I2C */

10
hw/arm/aspeed_ast2600.c
View file

@ -362,6 +362,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
qemu_irq irq;
g_autofree char *sram_name = NULL;
int uart;
/* Default boot region (SPI memory or ROMs) */
memory_region_init(&s->spi_boot_container, OBJECT(s),
@ -488,8 +489,13 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
aspeed_soc_get_irq(s, ASPEED_DEV_ADC));
/* UART */
if (!aspeed_soc_uart_realize(s, errp)) {
return;
for (i = 0, uart = sc->uarts_base; i < sc->uarts_num; i++, uart++) {
if (!aspeed_soc_uart_realize(s->memory, &s->uart[i],
sc->memmap[uart], errp)) {
return;
}
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
aspeed_soc_get_irq(s, uart));
}
/* I2C */

10
hw/arm/aspeed_ast27x0-ssp.c
View file

@ -164,6 +164,7 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
DeviceState *armv7m;
g_autofree char *sram_name = NULL;
int uart;
int i;
if (!clock_has_source(s->sysclk)) {
@ -237,8 +238,13 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), i));
}
/* UART */
if (!aspeed_soc_uart_realize(s, errp)) {
return;
for (i = 0, uart = sc->uarts_base; i < sc->uarts_num; i++, uart++) {
if (!aspeed_soc_uart_realize(s->memory, &s->uart[i],
sc->memmap[uart], errp)) {
return;
}
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
aspeed_soc_get_irq(s, uart));
}
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->timerctrl),

10
hw/arm/aspeed_ast27x0-tsp.c
View file

@ -164,6 +164,7 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
DeviceState *armv7m;
g_autofree char *sram_name = NULL;
int uart;
int i;
if (!clock_has_source(s->sysclk)) {
@ -237,8 +238,13 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), i));
}
/* UART */
if (!aspeed_soc_uart_realize(s, errp)) {
return;
for (i = 0, uart = sc->uarts_base; i < sc->uarts_num; i++, uart++) {
if (!aspeed_soc_uart_realize(s->memory, &s->uart[i],
sc->memmap[uart], errp)) {
return;
}
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
aspeed_soc_get_irq(s, uart));
}
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->timerctrl),

10
hw/arm/aspeed_ast27x0.c
View file

@ -687,6 +687,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
AspeedINTCClass *icio = ASPEED_INTC_GET_CLASS(&a->intc[1]);
g_autofree char *name = NULL;
qemu_irq irq;
int uart;
/* Default boot region (SPI memory or ROMs) */
memory_region_init(&s->spi_boot_container, OBJECT(s),
@ -788,8 +789,13 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
sc->memmap[ASPEED_DEV_SCUIO]);
/* UART */
if (!aspeed_soc_uart_realize(s, errp)) {
return;
for (i = 0, uart = sc->uarts_base; i < sc->uarts_num; i++, uart++) {
if (!aspeed_soc_uart_realize(s->memory, &s->uart[i],
sc->memmap[uart], errp)) {
return;
}
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
aspeed_soc_get_irq(s, uart));
}
/* FMC, The number of CS is set at the board level */

28
hw/arm/aspeed_soc_common.c
View file

@ -35,27 +35,19 @@ qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)
return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev);
}
bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp)
bool aspeed_soc_uart_realize(MemoryRegion *memory, SerialMM *smm,
const hwaddr addr, Error **errp)
{
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
SerialMM *smm;
for (int i = 0, uart = sc->uarts_base; i < sc->uarts_num; i++, uart++) {
smm = &s->uart[i];
/* Chardev property is set by the machine. */
qdev_prop_set_uint8(DEVICE(smm), "regshift", 2);
qdev_prop_set_uint32(DEVICE(smm), "baudbase", 38400);
qdev_set_legacy_instance_id(DEVICE(smm), sc->memmap[uart], 2);
qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN);
if (!sysbus_realize(SYS_BUS_DEVICE(smm), errp)) {
return false;
}
sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, aspeed_soc_get_irq(s, uart));
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(smm), 0, sc->memmap[uart]);
/* Chardev property is set by the machine. */
qdev_prop_set_uint8(DEVICE(smm), "regshift", 2);
qdev_prop_set_uint32(DEVICE(smm), "baudbase", 38400);
qdev_set_legacy_instance_id(DEVICE(smm), addr, 2);
qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN);
if (!sysbus_realize(SYS_BUS_DEVICE(smm), errp)) {
return false;
}
aspeed_mmio_map(memory, SYS_BUS_DEVICE(smm), 0, addr);
return true;
}

3
include/hw/arm/aspeed_soc.h
View file

@ -304,7 +304,8 @@ enum {
const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types);
qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev);
bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp);
bool aspeed_soc_uart_realize(MemoryRegion *memory, SerialMM *smm,
const hwaddr addr, Error **errp);
void aspeed_soc_uart_set_chr(SerialMM *uart, int dev, int uarts_base,
int uarts_num, Chardev *chr);
bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp);