fridtjof/qemu-cr16
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

target/arm: Populate PIE in aa64_va_parameters

Browse source 
Select the PIE bit for the translation regime.
With PIE, the PTE layout changes, forcing HPD.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20251008215613.300150-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2025-10-08 14:55:07 -07:00 • committed by Peter Maydell
parent 67f3eda009
commit 1952f58f98
2 changed files with 20 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

19
target/arm/helper.c
View file

@ -9386,11 +9386,12 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
bool el1_is_aa32)
{
uint64_t tcr = regime_tcr(env, mmu_idx);
bool epd, hpd, tsz_oob, ds, ha, hd;
bool epd, hpd, tsz_oob, ds, ha, hd, pie = false;
int select, tsz, tbi, max_tsz, min_tsz, ps, sh;
ARMGranuleSize gran;
ARMCPU *cpu = env_archcpu(env);
bool stage2 = regime_is_stage2(mmu_idx);
int r_el = regime_el(env, mmu_idx);
if (!regime_has_2_ranges(mmu_idx)) {
select = 0;
@ -9402,8 +9403,17 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
* Thus disabling them makes things easier during ptw.
*/
hpd = true;
pie = extract64(tcr, 36, 1) && cpu_isar_feature(aa64_s2pie, cpu);
} else {
hpd = extract32(tcr, 24, 1);
if (r_el == 3) {
pie = (extract64(tcr, 35, 1)
&& cpu_isar_feature(aa64_s1pie, cpu));
} else {
pie = ((env->cp15.tcr2_el[2] & TCR2_PIE)
&& (!arm_feature(env, ARM_FEATURE_EL3)
|| (env->cp15.scr_el3 & SCR_TCR2EN)));
}
}
epd = false;
sh = extract32(tcr, 12, 2);
@ -9443,7 +9453,13 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
regime_is_user(env, mmu_idx)) {
epd = true;
}
pie = ((env->cp15.tcr2_el[r_el] & TCR2_PIE)
&& (!arm_feature(env, ARM_FEATURE_EL3)
|| (env->cp15.scr_el3 & SCR_TCR2EN))
&& (r_el == 2 || (arm_hcrx_el2_eff(env) & HCRX_TCR2EN)));
}
hpd |= pie;
gran = sanitize_gran_size(cpu, gran, stage2);
@ -9522,6 +9538,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
.ha = ha,
.hd = ha && hd,
.gran = gran,
.pie = pie,
};
}

3
target/arm/internals.h
View file

@ -1491,7 +1491,7 @@ static inline int arm_granule_bits(ARMGranuleSize gran)
/*
* Parameters of a given virtual address, as extracted from the
* translation control register (TCR) for a given regime.
* translation controls for a given regime.
*/
typedef struct ARMVAParameters {
unsigned tsz : 8;
@ -1506,6 +1506,7 @@ typedef struct ARMVAParameters {
bool ha : 1;
bool hd : 1;
ARMGranuleSize gran : 2;
bool pie : 1;
} ARMVAParameters;
/**