diff --git a/target/cr16c/cpu.c b/target/cr16c/cpu.c index 8d7df6d9b6..3f882573a6 100644 --- a/target/cr16c/cpu.c +++ b/target/cr16c/cpu.c @@ -54,11 +54,11 @@ static void cr16c_cpu_reset_hold(Object *obj, ResetType type) env->r[0] = env->pc; env->r[1] = env->pc >> 16; - env->f_n = 0; - env->f_z = 0; - env->f_f = 0; - env->f_l = 0; - env->f_c = 0; + env->psr_n = 0; + env->psr_z = 0; + env->psr_f = 0; + env->psr_l = 0; + env->psr_c = 0; // TODO: Rest of flags from PSR once implemented env->pc = 0; @@ -97,11 +97,11 @@ static void cr16c_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, "SP: " TARGET_FMT_lx "\n", env->r[CR16C_REGNO_SP]); qemu_fprintf(f, "-- Flags --\n"); - qemu_fprintf(f, "N: %2d\n", env->f_n); - qemu_fprintf(f, "Z: %2d\n", env->f_z); - qemu_fprintf(f, "F: %2d\n", env->f_f); - qemu_fprintf(f, "L: %2d\n", env->f_l); - qemu_fprintf(f, "C: %2d\n", env->f_c); + qemu_fprintf(f, "N: %2d\n", env->psr_n); + qemu_fprintf(f, "Z: %2d\n", env->psr_z); + qemu_fprintf(f, "F: %2d\n", env->psr_f); + qemu_fprintf(f, "L: %2d\n", env->psr_l); + qemu_fprintf(f, "C: %2d\n", env->psr_c); qemu_fprintf(f, "\n"); } diff --git a/target/cr16c/cpu.h b/target/cr16c/cpu.h index a6f8cb017d..f6f54aee57 100644 --- a/target/cr16c/cpu.h +++ b/target/cr16c/cpu.h @@ -25,11 +25,11 @@ typedef struct CPUArchState { uint32_t r[CR16C_REG_COUNT]; /* General purpose registers: 12x16-bit + 2x32-bit */ - uint32_t f_n; - uint32_t f_z; - uint32_t f_f; - uint32_t f_l; - uint32_t f_c; + uint32_t psr_n; + uint32_t psr_z; + uint32_t psr_f; + uint32_t psr_l; + uint32_t psr_c; } CPUCR16CState; struct ArchCPU { diff --git a/target/cr16c/machine.c b/target/cr16c/machine.c index 7e89d64964..fa65d7a90b 100644 --- a/target/cr16c/machine.c +++ b/target/cr16c/machine.c @@ -8,11 +8,11 @@ const VMStateDescription vms_cr16c_cpu = { .fields = (VMStateField[]) { VMSTATE_UINT32(env.pc, CR16CCPU), VMSTATE_UINT32_ARRAY(env.r, CR16CCPU, CR16C_REG_COUNT), - VMSTATE_UINT32(env.f_n, CR16CCPU), - VMSTATE_UINT32(env.f_z, CR16CCPU), - VMSTATE_UINT32(env.f_f, CR16CCPU), - VMSTATE_UINT32(env.f_l, CR16CCPU), - VMSTATE_UINT32(env.f_c, CR16CCPU), + VMSTATE_UINT32(env.psr_n, CR16CCPU), + VMSTATE_UINT32(env.psr_z, CR16CCPU), + VMSTATE_UINT32(env.psr_f, CR16CCPU), + VMSTATE_UINT32(env.psr_l, CR16CCPU), + VMSTATE_UINT32(env.psr_c, CR16CCPU), VMSTATE_END_OF_LIST(), } }; diff --git a/target/cr16c/translate.c b/target/cr16c/translate.c index f61499b725..6066dc6936 100644 --- a/target/cr16c/translate.c +++ b/target/cr16c/translate.c @@ -45,11 +45,11 @@ typedef struct DisasContext { /* Registers */ static TCGv pc; -static TCGv f_n; -static TCGv f_z; -static TCGv f_f; -static TCGv f_l; -static TCGv f_c; +static TCGv psr_n; +static TCGv psr_z; +static TCGv psr_f; +static TCGv psr_l; +static TCGv psr_c; static TCGv r[CR16C_REG_COUNT]; @@ -241,22 +241,22 @@ static void gen_ADD_imm(TCGv_i32 rd, int32_t imm, bool add_carry, uint8_t width) tcg_gen_addi_i32(temp, temp, imm & ((1 << width * 8) - 1)); if(add_carry) { - tcg_gen_andi_i32(f_c, f_c, 1); - tcg_gen_add_i32(temp, temp, f_c); + tcg_gen_andi_i32(psr_c, psr_c, 1); + tcg_gen_add_i32(temp, temp, psr_c); } /* Carry flag */ - tcg_gen_shri_i32(f_c, temp, width * 8); + tcg_gen_shri_i32(psr_c, temp, width * 8); /* Overflow flag */ - tcg_gen_xor_i32(f_f, temp, rd); + tcg_gen_xor_i32(psr_f, temp, rd); if(imm < 0) { - tcg_gen_and_i32(f_f, f_f, rd); + tcg_gen_and_i32(psr_f, psr_f, rd); } else { - tcg_gen_andc_i32(f_f, f_f, rd); + tcg_gen_andc_i32(psr_f, psr_f, rd); } - tcg_gen_shri_i32(f_f, f_f, width*8 - 1); + tcg_gen_shri_i32(psr_f, psr_f, width*8 - 1); tcg_gen_deposit_i32(rd, rd, temp, 0, width*8); } @@ -277,19 +277,19 @@ static void gen_ADD_reg(TCGv reg1, TCGv reg2, bool plus_carry, uint8_t width) { tcg_gen_add_i32(temp1, temp1, temp2); if(plus_carry) { - tcg_gen_andi_i32(f_c, f_c, 1); - tcg_gen_add_i32(temp1, temp1, f_c); + tcg_gen_andi_i32(psr_c, psr_c, 1); + tcg_gen_add_i32(temp1, temp1, psr_c); } tcg_gen_deposit_i32(reg1, reg1, temp1, 0, width*8); /* Carry flag */ - tcg_gen_shri_i32(f_c, temp1, width*8); + tcg_gen_shri_i32(psr_c, temp1, width*8); /* Overflow flag */ - tcg_gen_xor_i32(f_f, reg1, reg2); - tcg_gen_and_i32(f_f, f_f, tempf_f); - tcg_gen_shri_i32(f_f, f_f, width*8-1); + tcg_gen_xor_i32(psr_f, reg1, reg2); + tcg_gen_and_i32(psr_f, psr_f, tempf_f); + tcg_gen_shri_i32(psr_f, psr_f, width*8-1); } static void gen_ADDD_imm(int regnl, int32_t imm) { @@ -312,16 +312,16 @@ static void gen_ADDD_imm(int regnl, int32_t imm) { tcg_gen_extrl_i64_i32(regl, temp_res); /* Carry flag */ - tcg_gen_extrh_i64_i32(f_c, temp_res); + tcg_gen_extrh_i64_i32(psr_c, temp_res); /* Overflow flag */ if (imm < 0) { - tcg_gen_andc_i32(f_f, temp_h, regl); + tcg_gen_andc_i32(psr_f, temp_h, regl); } else { - tcg_gen_andc_i32(f_f, regl, temp_h); + tcg_gen_andc_i32(psr_f, regl, temp_h); } - tcg_gen_shri_i32(f_f, f_f, 31); + tcg_gen_shri_i32(psr_f, psr_f, 31); if (regnl < CR16C_FIRST_32B_REG) { tcg_gen_shri_i32(regh, regl, 16); @@ -348,7 +348,7 @@ static bool gen_ADDD_rp(int rdn, TCGv_i32 rs, bool plus_one) { tcg_gen_extu_i32_i64(temp2, temp2_32); /* Prepare overflow flag */ - tcg_gen_xor_i32(f_f, temp2_32, rs); + tcg_gen_xor_i32(psr_f, temp2_32, rs); tcg_gen_add_i64(temp1, temp1, temp2); if(plus_one) { @@ -361,12 +361,12 @@ static bool gen_ADDD_rp(int rdn, TCGv_i32 rs, bool plus_one) { } /* Carry flag */ - tcg_gen_extrh_i64_i32(f_c, temp1); + tcg_gen_extrh_i64_i32(psr_c, temp1); /* Overflow flag */ tcg_gen_xor_i32(temp2_32, temp2_32, rdl); - tcg_gen_andc_i32(f_f, temp2_32, f_f); - tcg_gen_shri_i32(f_f, f_f, 31); + tcg_gen_andc_i32(psr_f, temp2_32, psr_f); + tcg_gen_shri_i32(psr_f, psr_f, 31); return true; } @@ -488,24 +488,24 @@ static bool trans_SUB_imm(DisasContext *ctx, arg_SUB_imm *a) { int32_t imm = -a->imm; if (a->add_carry) { imm--; - tcg_gen_xori_i32(f_c, f_c, 1); + tcg_gen_xori_i32(psr_c, psr_c, 1); } gen_ADD_imm(r[a->rd], imm, a->add_carry, a->width); - tcg_gen_xori_i32(f_c, f_c, 1); + tcg_gen_xori_i32(psr_c, psr_c, 1); return true; } static bool trans_SUB_reg(DisasContext *ctx, arg_SUB_reg *a) { TCGv_i32 temp = tcg_temp_new_i32(); if (a->add_carry) { - tcg_gen_xori_i32(f_c, f_c, 1); + tcg_gen_xori_i32(psr_c, psr_c, 1); tcg_gen_xori_i32(temp, r[a->rs], (1 << (a->width*8)) - 1); } else { tcg_gen_neg_i32(temp, r[a->rs]); } gen_ADD_reg(r[a->rd], temp, a->add_carry, a->width); - tcg_gen_xori_i32(f_c, f_c, 1); + tcg_gen_xori_i32(psr_c, psr_c, 1); return true; } @@ -516,13 +516,13 @@ static bool trans_SUBD_rp(DisasContext *ctx, arg_SUBD_rp *a) { } tcg_gen_xori_i32(templ, r[a->rs], 0xFFFFFFFF); gen_ADDD_rp(a->rd, templ, true); - tcg_gen_xori_i32(f_c, f_c, 1); + tcg_gen_xori_i32(psr_c, psr_c, 1); return true; } static bool trans_SUBD_imm(DisasContext *ctx, arg_SUBD_imm *a) { gen_ADDD_imm(a->rd, -a->imm); - tcg_gen_xori_i32(f_c, f_c, 1); + tcg_gen_xori_i32(psr_c, psr_c, 1); return true; } @@ -651,9 +651,9 @@ static bool trans_MACSW(DisasContext *ctx, arg_MACSW *a) { /* Integer Comparison */ static void gen_cmp(TCGv_i32 src1, TCGv_i32 src2) { - tcg_gen_setcond_i32(TCG_COND_EQ, f_z, src1, src2); - tcg_gen_setcond_i32(TCG_COND_GT, f_l, src1, src2); - tcg_gen_setcond_i32(TCG_COND_GTU, f_n, src1, src2); + tcg_gen_setcond_i32(TCG_COND_EQ, psr_z, src1, src2); + tcg_gen_setcond_i32(TCG_COND_GT, psr_l, src1, src2); + tcg_gen_setcond_i32(TCG_COND_GTU, psr_n, src1, src2); } static bool trans_CMP_imm(DisasContext *ctx, arg_CMP_imm *a) { @@ -835,48 +835,48 @@ static bool trans_XORD_rp(DisasContext *ctx, arg_XORD_rp *a) { static bool trans_SCOND(DisasContext *ctx, arg_SCOND *a) { switch (a->imm) { case CR16C_COND_EQ: - tcg_gen_andi_i32(r[a->rd], f_z, 1); + tcg_gen_andi_i32(r[a->rd], psr_z, 1); break; case CR16C_COND_NE: - tcg_gen_andc_i32(r[a->rd], tcg_constant_i32(1), f_z); + tcg_gen_andc_i32(r[a->rd], tcg_constant_i32(1), psr_z); break; case CR16C_COND_CS: - tcg_gen_andi_i32(r[a->rd], f_c, 1); + tcg_gen_andi_i32(r[a->rd], psr_c, 1); break; case CR16C_COND_CC: - tcg_gen_andc_i32(r[a->rd], tcg_constant_i32(1), f_c); + tcg_gen_andc_i32(r[a->rd], tcg_constant_i32(1), psr_c); break; case CR16C_COND_HI: - tcg_gen_mov_i32(r[a->rd], f_l); + tcg_gen_mov_i32(r[a->rd], psr_l); break; case CR16C_COND_LS: - tcg_gen_andc_i32(r[a->rd], tcg_constant_i32(1), f_l); + tcg_gen_andc_i32(r[a->rd], tcg_constant_i32(1), psr_l); break; case CR16C_COND_GT: - tcg_gen_mov_i32(r[a->rd], f_n); + tcg_gen_mov_i32(r[a->rd], psr_n); break; case CR16C_COND_LE: - tcg_gen_andc_i32(r[a->rd], tcg_constant_i32(1), f_n); + tcg_gen_andc_i32(r[a->rd], tcg_constant_i32(1), psr_n); break; case CR16C_COND_FS: - tcg_gen_andi_i32(r[a->rd], f_f, 1); + tcg_gen_andi_i32(r[a->rd], psr_f, 1); break; case CR16C_COND_FC: - tcg_gen_andc_i32(r[a->rd], tcg_constant_i32(1), f_f); + tcg_gen_andc_i32(r[a->rd], tcg_constant_i32(1), psr_f); break; case CR16C_COND_LO: - tcg_gen_nor_i32(r[a->rd], f_z, f_l); + tcg_gen_nor_i32(r[a->rd], psr_z, psr_l); tcg_gen_andi_i32(r[a->rd], r[a->rd], 1); break; case CR16C_COND_HS: - tcg_gen_or_i32(r[a->rd], f_z, f_l); + tcg_gen_or_i32(r[a->rd], psr_z, psr_l); break; case CR16C_COND_LT: - tcg_gen_nor_i32(r[a->rd], f_z, f_n); + tcg_gen_nor_i32(r[a->rd], psr_z, psr_n); tcg_gen_andi_i32(r[a->rd], r[a->rd], 1); break; case CR16C_COND_GE: - tcg_gen_or_i32(r[a->rd], f_z, f_n); + tcg_gen_or_i32(r[a->rd], psr_z, psr_n); break; } @@ -1078,20 +1078,20 @@ static bool trans_LSHD_rp(DisasContext *ctx, arg_LSHD_rp *a) { static void gen_CBIT(TCGv_i32 addr, uint8_t pos, uint8_t width) { uint32_t mask = ~(1 << pos); MemOp memop = width == 2 ? MO_UW : MO_UB; - tcg_gen_atomic_fetch_and_i32(f_f, addr, tcg_constant_i32(mask), 0, memop); - tcg_gen_shri_i32(f_f, f_f, pos); + tcg_gen_atomic_fetch_and_i32(psr_f, addr, tcg_constant_i32(mask), 0, memop); + tcg_gen_shri_i32(psr_f, psr_f, pos); } static void gen_SBIT(TCGv_i32 addr, uint8_t pos, uint8_t width) { uint32_t mask = 1 << pos; MemOp memop = width == 2 ? MO_UW : MO_UB; - tcg_gen_atomic_fetch_or_i32(f_f, addr, tcg_constant_i32(mask), 0, memop); - tcg_gen_shri_i32(f_f, f_f, pos); + tcg_gen_atomic_fetch_or_i32(psr_f, addr, tcg_constant_i32(mask), 0, memop); + tcg_gen_shri_i32(psr_f, psr_f, pos); } static bool gen_TBIT_mem(TCGv_i32 addr, uint8_t pos, uint8_t width) { - tcg_gen_qemu_ld_i32(f_f, addr, 0, unsigned_op_by_width[width]); - tcg_gen_shri_i32(f_f, f_f, pos); + tcg_gen_qemu_ld_i32(psr_f, addr, 0, unsigned_op_by_width[width]); + tcg_gen_shri_i32(psr_f, psr_f, pos); return true; } @@ -1171,13 +1171,13 @@ static bool trans_TBIT_mem_abs(DisasContext *ctx, arg_TBIT_mem_abs *a) { static bool trans_TBIT_reg_imm(DisasContext *ctx, arg_TBIT_reg_imm *a) { - tcg_gen_shri_i32(f_f, r[a->rs], a->pos); + tcg_gen_shri_i32(psr_f, r[a->rs], a->pos); return true; } static bool trans_TBIT_reg_reg(DisasContext *ctx, arg_TBIT_reg_reg *a) { - tcg_gen_shr_i32(f_f, r[a->rs], r[a->rp]); + tcg_gen_shr_i32(psr_f, r[a->rs], r[a->rp]); return true; } @@ -1198,61 +1198,61 @@ static void gen_br_cond(DisasContext* ctx, int cond, TCGLabel* l) { TCGv temp; /* Flags may have higher bits set */ - tcg_gen_andi_i32(f_n, f_n, 1); - tcg_gen_andi_i32(f_z, f_z, 1); - tcg_gen_andi_i32(f_f, f_f, 1); - tcg_gen_andi_i32(f_l, f_l, 1); - tcg_gen_andi_i32(f_c, f_c, 1); + tcg_gen_andi_i32(psr_n, psr_n, 1); + tcg_gen_andi_i32(psr_z, psr_z, 1); + tcg_gen_andi_i32(psr_f, psr_f, 1); + tcg_gen_andi_i32(psr_l, psr_l, 1); + tcg_gen_andi_i32(psr_c, psr_c, 1); switch (cond) { case CR16C_COND_EQ: - tcg_gen_brcondi_i32(TCG_COND_EQ, f_z, 1, l); + tcg_gen_brcondi_i32(TCG_COND_EQ, psr_z, 1, l); break; case CR16C_COND_NE: - tcg_gen_brcondi_i32(TCG_COND_NE, f_z, 1, l); + tcg_gen_brcondi_i32(TCG_COND_NE, psr_z, 1, l); break; case CR16C_COND_CS: - tcg_gen_brcondi_i32(TCG_COND_EQ, f_c, 1, l); + tcg_gen_brcondi_i32(TCG_COND_EQ, psr_c, 1, l); break; case CR16C_COND_CC: - tcg_gen_brcondi_i32(TCG_COND_NE, f_c, 1, l); + tcg_gen_brcondi_i32(TCG_COND_NE, psr_c, 1, l); break; case CR16C_COND_HI: - tcg_gen_brcondi_i32(TCG_COND_EQ, f_l, 1, l); + tcg_gen_brcondi_i32(TCG_COND_EQ, psr_l, 1, l); break; case CR16C_COND_LS: - tcg_gen_brcondi_i32(TCG_COND_NE, f_l, 1, l); + tcg_gen_brcondi_i32(TCG_COND_NE, psr_l, 1, l); break; case CR16C_COND_GT: - tcg_gen_brcondi_i32(TCG_COND_EQ, f_n, 1, l); + tcg_gen_brcondi_i32(TCG_COND_EQ, psr_n, 1, l); break; case CR16C_COND_LE: - tcg_gen_brcondi_i32(TCG_COND_NE, f_n, 1, l); + tcg_gen_brcondi_i32(TCG_COND_NE, psr_n, 1, l); break; case CR16C_COND_FS: - tcg_gen_brcondi_i32(TCG_COND_EQ, f_f, 1, l); + tcg_gen_brcondi_i32(TCG_COND_EQ, psr_f, 1, l); break; case CR16C_COND_FC: - tcg_gen_brcondi_i32(TCG_COND_NE, f_f, 1, l); + tcg_gen_brcondi_i32(TCG_COND_NE, psr_f, 1, l); break; case CR16C_COND_LO: temp = tcg_temp_new_i32(); - tcg_gen_or_i32(temp, f_z, f_l); + tcg_gen_or_i32(temp, psr_z, psr_l); tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l); break; case CR16C_COND_HS: temp = tcg_temp_new_i32(); - tcg_gen_and_i32(temp, f_z, f_l); + tcg_gen_and_i32(temp, psr_z, psr_l); tcg_gen_brcondi_i32(TCG_COND_NE, temp, 1, l); break; case CR16C_COND_LT: temp = tcg_temp_new_i32(); - tcg_gen_or_i32(temp, f_z, f_n); + tcg_gen_or_i32(temp, psr_z, psr_n); tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l); break; case CR16C_COND_GE: temp = tcg_temp_new_i32(); - tcg_gen_and_i32(temp, f_z, f_n); + tcg_gen_and_i32(temp, psr_z, psr_n); tcg_gen_brcondi_i32(TCG_COND_NE, temp, 1, l); break; case CR16C_COND_ALWAYS: @@ -1507,11 +1507,11 @@ void cr16c_translate_init(void) { r[i] = tcg_global_mem_new_i32(tcg_env, offsetof(CPUCR16CState, r[i]), cr16c_cpu_r_names[i]); } pc = tcg_global_mem_new_i32(tcg_env, offsetof(CPUCR16CState, pc), "pc"); - f_n = tcg_global_mem_new_i32(tcg_env, offsetof(CPUCR16CState, f_n), "f_n"); - f_z = tcg_global_mem_new_i32(tcg_env, offsetof(CPUCR16CState, f_z), "f_z"); - f_f = tcg_global_mem_new_i32(tcg_env, offsetof(CPUCR16CState, f_f), "f_f"); - f_l = tcg_global_mem_new_i32(tcg_env, offsetof(CPUCR16CState, f_l), "f_l"); - f_c = tcg_global_mem_new_i32(tcg_env, offsetof(CPUCR16CState, f_c), "f_c"); + psr_n = tcg_global_mem_new_i32(tcg_env, offsetof(CPUCR16CState, psr_n), "psr_n"); + psr_z = tcg_global_mem_new_i32(tcg_env, offsetof(CPUCR16CState, psr_z), "psr_z"); + psr_f = tcg_global_mem_new_i32(tcg_env, offsetof(CPUCR16CState, psr_f), "psr_f"); + psr_l = tcg_global_mem_new_i32(tcg_env, offsetof(CPUCR16CState, psr_l), "psr_l"); + psr_c = tcg_global_mem_new_i32(tcg_env, offsetof(CPUCR16CState, psr_c), "psr_c"); } void cr16c_translate_code(CPUState *cs, TranslationBlock *tb,