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target/ppc: Move remaining floating-point move instructions to decodetree.

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Move below instructions to decodetree specification:

	fcpsgn, fmrg{e, o}w	: X-form

The changes were verified by validating that the tcg ops generated by
those instructions remain the same, which were captured with the '-d
in_asm,op' flag.

Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Link: https://lore.kernel.org/r/20250619095840.369351-5-rathc@linux.ibm.com
Message-ID: <20250619095840.369351-5-rathc@linux.ibm.com>
This commit is contained in:
Chinmay Rath 2025-06-19 15:28:39 +05:30 • committed by Harsh Prateek Bora
parent 5c89a201a9
commit 241f6f7994
No known key found for this signature in database
GPG key ID: 4544E994F9D68FBB
3 changed files with 37 additions and 45 deletions
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4
target/ppc/insn32.decode
View file

@ -537,6 +537,10 @@ FNEG 111111 ..... ----- ..... 0000101000 . @X_tb_rc
FABS 111111 ..... ----- ..... 0100001000 . @X_tb_rc
FNABS 111111 ..... ----- ..... 0010001000 . @X_tb_rc
FCPSGN 111111 ..... ..... ..... 0000001000 . @X_rc
FMRGEW 111111 ..... ..... ..... 1111000110 - @X
FMRGOW 111111 ..... ..... ..... 1101000110 - @X
### Floating-Point Arithmetic Instructions
FADD 111111 ..... ..... ..... ----- 10101 . @A_tab

75
target/ppc/translate/fp-impl.c.inc
View file

@ -321,62 +321,53 @@ TRANS(FNABS, do_move_b, 1ULL << 63, tcg_gen_ori_i64);
/* fcpsgn: PowerPC 2.05 specification */
/* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
static void gen_fcpsgn(DisasContext *ctx)
static bool trans_FCPSGN(DisasContext *ctx, arg_FCPSGN *a)
{
TCGv_i64 t0;
TCGv_i64 t1;
TCGv_i64 t2;
if (unlikely(!ctx->fpu_enabled)) {
gen_exception(ctx, POWERPC_EXCP_FPU);
return;
}
TCGv_i64 t0, t1, t2;
REQUIRE_INSNS_FLAGS2(ctx, ISA205);
REQUIRE_FPU(ctx);
t0 = tcg_temp_new_i64();
t1 = tcg_temp_new_i64();
t2 = tcg_temp_new_i64();
get_fpr(t0, rA(ctx->opcode));
get_fpr(t1, rB(ctx->opcode));
get_fpr(t0, a->ra);
get_fpr(t1, a->rb);
tcg_gen_deposit_i64(t2, t0, t1, 0, 63);
set_fpr(rD(ctx->opcode), t2);
if (unlikely(Rc(ctx->opcode))) {
set_fpr(a->rt, t2);
if (unlikely(a->rc)) {
gen_set_cr1_from_fpscr(ctx);
}
return true;
}
static void gen_fmrgew(DisasContext *ctx)
static bool trans_FMRGEW(DisasContext *ctx, arg_FMRGEW *a)
{
TCGv_i64 b0;
TCGv_i64 t0;
TCGv_i64 t1;
if (unlikely(!ctx->fpu_enabled)) {
gen_exception(ctx, POWERPC_EXCP_FPU);
return;
}
b0 = tcg_temp_new_i64();
t0 = tcg_temp_new_i64();
t1 = tcg_temp_new_i64();
get_fpr(t0, rB(ctx->opcode));
tcg_gen_shri_i64(b0, t0, 32);
get_fpr(t0, rA(ctx->opcode));
tcg_gen_deposit_i64(t1, t0, b0, 0, 32);
set_fpr(rD(ctx->opcode), t1);
}
static void gen_fmrgow(DisasContext *ctx)
{
TCGv_i64 t0;
TCGv_i64 t1;
TCGv_i64 t2;
if (unlikely(!ctx->fpu_enabled)) {
gen_exception(ctx, POWERPC_EXCP_FPU);
return;
}
TCGv_i64 t0, t1, t2;
REQUIRE_INSNS_FLAGS2(ctx, VSX207);
REQUIRE_FPU(ctx);
t0 = tcg_temp_new_i64();
t1 = tcg_temp_new_i64();
t2 = tcg_temp_new_i64();
get_fpr(t0, rB(ctx->opcode));
get_fpr(t1, rA(ctx->opcode));
get_fpr(t1, a->rb);
tcg_gen_shri_i64(t0, t1, 32);
get_fpr(t1, a->ra);
tcg_gen_deposit_i64(t2, t1, t0, 0, 32);
set_fpr(a->rt, t2);
return true;
}
static bool trans_FMRGOW(DisasContext *ctx, arg_FMRGOW *a)
{
TCGv_i64 t0, t1, t2;
REQUIRE_INSNS_FLAGS2(ctx, VSX207);
REQUIRE_FPU(ctx);
t0 = tcg_temp_new_i64();
t1 = tcg_temp_new_i64();
t2 = tcg_temp_new_i64();
get_fpr(t0, a->rb);
get_fpr(t1, a->ra);
tcg_gen_deposit_i64(t2, t0, t1, 32, 32);
set_fpr(rD(ctx->opcode), t2);
set_fpr(a->rt, t2);
return true;
}
/*** Floating-Point status & ctrl register ***/

3
target/ppc/translate/fp-ops.c.inc
View file

@ -10,9 +10,6 @@ GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
GEN_HANDLER_E(stfdepx, 0x1F, 0x1F, 0x16, 0x00000001, PPC_NONE, PPC2_BOOKE206),
GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205),
GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207),
GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207),
GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),