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target/riscv: Fix fcvt.s.bf16 NaN box checking

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fcvt.s.bf16 uses the FP16 check_nanbox_h() which returns an FP16
quiet NaN. Add check_nanbox_bf16() which returns a BF16 quiet NaN.

Signed-off-by: Anton Blanchard <antonb@tenstorrent.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250501114253.594887-1-antonb@tenstorrent.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Anton Blanchard 2025-05-01 11:42:53 +00:00 • committed by Alistair Francis
parent 7ec39d0cc9
commit 2b027e73ee
2 changed files with 17 additions and 1 deletions
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2
target/riscv/fpu_helper.c
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@ -755,6 +755,6 @@ uint64_t helper_fcvt_bf16_s(CPURISCVState *env, uint64_t rs1)
uint64_t helper_fcvt_s_bf16(CPURISCVState *env, uint64_t rs1)
{
float16 frs1 = check_nanbox_h(env, rs1);
float16 frs1 = check_nanbox_bf16(env, rs1);
return nanbox_s(env, bfloat16_to_float32(frs1, &env->fp_status));
}

16
target/riscv/internals.h
View file

@ -142,6 +142,22 @@ static inline float16 check_nanbox_h(CPURISCVState *env, uint64_t f)
}
}
static inline float16 check_nanbox_bf16(CPURISCVState *env, uint64_t f)
{
/* Disable nanbox check when enable zfinx */
if (env_archcpu(env)->cfg.ext_zfinx) {
return (uint16_t)f;
}
uint64_t mask = MAKE_64BIT_MASK(16, 48);
if (likely((f & mask) == mask)) {
return (uint16_t)f;
} else {
return 0x7FC0u; /* default qnan */
}
}
#ifndef CONFIG_USER_ONLY
/* Our implementation of SysemuCPUOps::has_work */
bool riscv_cpu_has_work(CPUState *cs);