From 2b96aa2f411fb2492b30ced2b3af6cd81fbb1540 Mon Sep 17 00:00:00 2001
From: fridtjof <fridtjof@das-labor.org>
Date: Fri, 15 Aug 2025 01:35:35 +0200
Subject: [PATCH] wip! implement LPR(D), SPR(D) (stubs only)

---
 target/cr16c/insn.decode | 18 ++++++++++++++++++
 target/cr16c/translate.c | 20 ++++++++++++++++++++
 2 files changed, 38 insertions(+)

diff --git a/target/cr16c/insn.decode b/target/cr16c/insn.decode
index e77c56e9e2..33469c0db1 100644
--- a/target/cr16c/insn.decode
+++ b/target/cr16c/insn.decode
@@ -442,3 +442,21 @@ LOADM  0000 0000 1010 0...  pair=0   @ldstm
 LOADM  0000 0000 1010 1...  pair=1   @ldstm
 STORM  0000 0000 1011 0...  pair=0   @ldstm
 STORM  0000 0000 1011 1...  pair=1   @ldstm
+
+# Processor Register Manipulation
+#LPR Rsrc, Rproc Load processor register
+#LPRD RPsrc, Rprocd Load double processor register
+#SPR Rproc, Rdest Store processor register
+#SPRD Rprocd, RPdest Store double processor register
+
+# fmt escape2
+
+# followed by another word p4_4(mode) p3_4(res) p2_4(pr) p1_4(reg)
+&lp_sp  p2 p1
+@lp_sp  .... .... .... ....  .... .... p2:4 p1:4 &lp_sp
+
+#                            ope
+LPR     0000 0000 0001 0100  0000 0000 .... ....  @lp_sp
+LPRD    0000 0000 0001 0100  0001 0000 .... ....  @lp_sp
+SPR     0000 0000 0001 0100  0010 0000 .... ....  @lp_sp
+SPRD    0000 0000 0001 0100  0011 0000 .... ....  @lp_sp
diff --git a/target/cr16c/translate.c b/target/cr16c/translate.c
index a4cb0a4bfe..4e1cfb8675 100644
--- a/target/cr16c/translate.c
+++ b/target/cr16c/translate.c
@@ -1482,6 +1482,26 @@ static bool trans_STORM(DisasContext *ctx, arg_STORM *a) {
     return true;
 }
 
+static bool trans_LPR(DisasContext *ctx, arg_LPR* a) {
+    gen_helper_raise_unimplemented_instruction();
+    return true;
+}
+
+static bool trans_LPRD(DisasContext *ctx, arg_LPRD* a) {
+    gen_helper_raise_unimplemented_instruction();
+    return true;
+}
+
+static bool trans_SPR(DisasContext *ctx, arg_SPR* a) {
+    gen_helper_raise_unimplemented_instruction();
+    return true;
+}
+
+static bool trans_SPRD(DisasContext *ctx, arg_SPRD* a) {
+    gen_helper_raise_unimplemented_instruction();
+    return true;
+}
+
 static bool trans_BAL_ra(DisasContext *ctx, arg_BAL_ra *a) {
 #define BAL_LEN 4
     // TODO BAL_rp would be 3 words/6 bytes (fmt 3a)