diff --git a/target/cr16c/cpu.c b/target/cr16c/cpu.c
index 0a629f0415..21a51689ae 100644
--- a/target/cr16c/cpu.c
+++ b/target/cr16c/cpu.c
@@ -85,7 +85,10 @@ static void cr16c_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 {
     CPUCR16CState* env = cpu_env(cs);
     qemu_fprintf(f, "-- Special purpose registers --\n");
-    qemu_fprintf(f, "PC:    " TARGET_FMT_lx "\n", env->pc);
+    qemu_fprintf(f, "PC:      " TARGET_FMT_lx "\n", env->pc);
+    qemu_fprintf(f, "INTBASE: " TARGET_FMT_lx "\n", env->intbase);
+    qemu_fprintf(f, "ISP:     " TARGET_FMT_lx "\n", env->isp);
+    qemu_fprintf(f, "USP:     " TARGET_FMT_lx "\n", env->usp);
 
     qemu_fprintf(f, "-- General purpose registers --\n");
     for(int i = 0; i < 10; i++) {
diff --git a/target/cr16c/cpu.h b/target/cr16c/cpu.h
index 4f7afba78c..52d46012dc 100644
--- a/target/cr16c/cpu.h
+++ b/target/cr16c/cpu.h
@@ -55,6 +55,10 @@ typedef struct CPUArchState {
 
     uint32_t r[CR16C_REG_COUNT]; /* General purpose registers: 12x16-bit + 2x32-bit */
 
+    uint32_t intbase;    // interrupt base (dispatch table)
+    uint32_t isp;   // interrupt stack pointer
+    uint32_t usp;    // user stack pointer
+
     uint32_t psr_n;     // Negative bit
     uint32_t psr_z;     // Zero bit
     uint32_t psr_f;     // Flag bit
diff --git a/target/cr16c/translate.c b/target/cr16c/translate.c
index 0430fe61b3..dcf85a49b9 100644
--- a/target/cr16c/translate.c
+++ b/target/cr16c/translate.c
@@ -67,9 +67,9 @@ typedef struct DisasContext {
 
 /* Registers */
 static TCGv pc; // 24 bit
-// ISPH/L (Interrupt Stack Pointer)
-// USPH/L (User Stack Pointer)
-// INTBASEH/L (Interrupt Base)
+static TCGv isp; // Interrupt Stack Pointer, 24 bit. lowest bit is always 0
+static TCGv usp; // User Stack Pointer
+static TCGv intbase; // Interrupt Base, 24 bit. lowest bit is always 0
 
 // PSR 16
 // these flags are part of PSR
@@ -1757,6 +1757,10 @@ void cr16c_translate_init(void) {
     for(int i = 0; i < CR16C_REG_COUNT; i++) {
         r[i] = tcg_global_mem_new_i32(tcg_env, offsetof(CPUCR16CState, r[i]), cr16c_cpu_r_names[i]);
     }
+    intbase = tcg_global_mem_new_i32(tcg_env, offsetof(CPUCR16CState, intbase), "intbase");
+    isp = tcg_global_mem_new_i32(tcg_env, offsetof(CPUCR16CState, isp), "isp");
+    usp = tcg_global_mem_new_i32(tcg_env, offsetof(CPUCR16CState, usp), "usp");
+
     pc = tcg_global_mem_new_i32(tcg_env, offsetof(CPUCR16CState, pc), "pc");
     psr_n = tcg_global_mem_new_i32(tcg_env, offsetof(CPUCR16CState, psr_n), "psr_n");
     psr_z = tcg_global_mem_new_i32(tcg_env, offsetof(CPUCR16CState, psr_z), "psr_z");