target/arm: Remove cp argument to ENCODE_AA64_CP_REG
All invocations were required to pass the same value, CP_REG_ARM64_SYSREG_CP. Bake that in to the result directly. Remove CP_REG_ARM64_SYSREG_CP as unused. Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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5 changed files with 10 additions and 18 deletions
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@ -187,9 +187,8 @@ enum {
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((is64) << CP_REG_AA32_64BIT_SHIFT) | \
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((cp) << 16) | ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
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#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
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(CP_REG_AA64_MASK | \
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((cp) << CP_REG_ARM_COPROC_SHIFT) | \
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#define ENCODE_AA64_CP_REG(crn, crm, op0, op1, op2) \
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(CP_REG_AA64_MASK | CP_REG_ARM64_SYSREG | \
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((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \
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((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \
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((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \
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@ -4503,7 +4503,7 @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
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};
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#define K(op0, op1, crn, crm, op2) \
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ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2)
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ENCODE_AA64_CP_REG(crn, crm, op0, op1, op2)
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static const struct E2HAlias aliases[] = {
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{ K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0),
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@ -7396,10 +7396,9 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
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* in their AArch64 view (the .cp value may be non-zero for the
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* benefit of the AArch32 view).
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*/
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if (cp == 0 || r->state == ARM_CP_STATE_BOTH) {
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cp = CP_REG_ARM64_SYSREG_CP;
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}
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key = ENCODE_AA64_CP_REG(cp, r->crn, crm, r->opc0, opc1, opc2);
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assert(cp == 0 || r->state == ARM_CP_STATE_BOTH);
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cp = 0;
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key = ENCODE_AA64_CP_REG(r->crn, crm, r->opc0, opc1, opc2);
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break;
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default:
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g_assert_not_reached();
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@ -7624,7 +7623,7 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *r)
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}
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break;
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case ARM_CP_STATE_AA64:
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assert(r->cp == 0 || r->cp == CP_REG_ARM64_SYSREG_CP);
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assert(r->cp == 0);
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break;
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default:
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g_assert_not_reached();
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@ -1124,8 +1124,7 @@ static bool is_id_sysreg(uint32_t reg)
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static uint32_t hvf_reg2cp_reg(uint32_t reg)
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{
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return ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP,
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(reg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK,
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return ENCODE_AA64_CP_REG((reg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK,
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(reg >> SYSREG_CRM_SHIFT) & SYSREG_CRM_MASK,
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(reg >> SYSREG_OP0_SHIFT) & SYSREG_OP0_MASK,
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(reg >> SYSREG_OP1_SHIFT) & SYSREG_OP1_MASK,
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@ -160,9 +160,6 @@ MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A53, KVM_ARM_TARGET_CORTEX_A53);
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#define CP_REG_ARM64_SYSREG_OP2_MASK 0x0000000000000007
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#define CP_REG_ARM64_SYSREG_OP2_SHIFT 0
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/* No kernel define but it's useful to QEMU */
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#define CP_REG_ARM64_SYSREG_CP (CP_REG_ARM64_SYSREG >> CP_REG_ARM_COPROC_SHIFT)
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MISMATCH_CHECK(CP_REG_ARM64, KVM_REG_ARM64);
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MISMATCH_CHECK(CP_REG_ARM_COPROC_MASK, KVM_REG_ARM_COPROC_MASK);
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MISMATCH_CHECK(CP_REG_ARM_COPROC_SHIFT, KVM_REG_ARM_COPROC_SHIFT);
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@ -2466,8 +2466,7 @@ static void handle_sys(DisasContext *s, bool isread,
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unsigned int op0, unsigned int op1, unsigned int op2,
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unsigned int crn, unsigned int crm, unsigned int rt)
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{
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uint32_t key = ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP,
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crn, crm, op0, op1, op2);
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uint32_t key = ENCODE_AA64_CP_REG(crn, crm, op0, op1, op2);
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const ARMCPRegInfo *ri = get_arm_cp_reginfo(s->cp_regs, key);
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bool need_exit_tb = false;
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bool nv_trap_to_el2 = false;
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@ -2603,8 +2602,7 @@ static void handle_sys(DisasContext *s, bool isread,
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* We don't use the EL1 register's access function, and
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* fine-grained-traps on EL1 also do not apply here.
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*/
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key = ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP,
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crn, crm, op0, 0, op2);
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key = ENCODE_AA64_CP_REG(crn, crm, op0, 0, op2);
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ri = get_arm_cp_reginfo(s->cp_regs, key);
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assert(ri);
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assert(cp_access_ok(s->current_el, ri, isread));
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