diff --git a/target/cr16c/insn.decode b/target/cr16c/insn.decode index a72f7cbad0..590ba1ba3c 100644 --- a/target/cr16c/insn.decode +++ b/target/cr16c/insn.decode @@ -1,6 +1,8 @@ %u4_load_s16 52:4 !function=u4_load_s16 %load_u16 !function=load_u16 +%addr_abs20 32:20 !function=reloc_abs20 +%addr_disp24 32:4 40:4 16:16 ### Moves ### @@ -156,6 +158,95 @@ LSHD_imm_r 0100 101. .... .... @shiftd_imm LSHD_rp 0100 0111 .... .... @shiftd_rp +### Bit operations ### + +&xbit_reg ra pos dbase disp width +&xbit_rrp rrp pos disp width +&xbit_abs addr pos width + +%xbit_disp14 40:6 46:2 52:2 32:4 +%xbit_disp20 40:4 16:s16 + +@xbit_disp14_rrp .... .... .... rrp:4 .... .... pos:4 .... disp=%xbit_disp14 &xbit_rrp +@xbit_disp20_reg .... .... .... .... .... .... pos:4 ra:4 .... .... .... .... disp=%xbit_disp20 &xbit_reg +@xbit_disp20_rrp .... .... .... .... .... .... pos:4 rrp:4 .... .... .... .... disp=%xbit_disp20 &xbit_rrp +@xbitb_disp0_rp .... .... . pos:3 ra:4 &xbit_reg +@xbitw_disp0_rp .... .... pos:4 ra:4 &xbit_reg +@xbitb_disp16_reg .... .... . pos:3 ra:4 disp:s16 &xbit_reg +@xbitw_disp16_reg .... .... pos:4 ra:4 disp:s16 &xbit_reg +@xbitb_abs20 .... .... . pos:3 .... .... .... .... .... addr=%addr_abs20 &xbit_abs +@xbitw_abs20 .... .... pos:4 .... .... .... .... .... addr=%addr_abs20 &xbit_abs +@xbitb_abs20_rel .... .... . pos:3 .... .... .... .... .... disp=%addr_abs20 &xbit_reg +@xbitw_abs20_rel .... .... pos:4 .... .... .... .... .... disp=%addr_abs20 &xbit_reg +@xbit_abs24 .... .... .... .... .... .... pos:4 .... .... .... .... .... addr=%addr_disp24 &xbit_abs + +CBIT_rrp 0110 1010 10.. .... .... .... .... .... width=1 @xbit_disp14_rrp +CBIT_reg 0000 0000 0001 0000 0100 .... .... .... .... .... .... .... width=1 dbase=0 @xbit_disp20_reg +CBIT_reg 0110 1010 0... .... width=1 dbase=1 disp=0 @xbitb_disp0_rp +CBIT_reg 0110 1011 0... .... .... .... .... .... width=1 dbase=1 @xbitb_disp16_reg +CBIT_reg 0000 0000 0001 0000 0101 .... .... .... .... .... .... .... width=1 dbase=1 @xbit_disp20_reg +CBIT_rrp 0000 0000 0001 0000 0110 .... .... .... .... .... .... .... width=1 @xbit_disp20_rrp +CBIT_abs 0110 1011 1... .... .... .... .... .... width=1 @xbitb_abs20 +CBIT_reg 0110 1000 0... .... .... .... .... .... width=1 dbase=1 ra=12 @xbitb_abs20_rel +CBIT_reg 0110 1000 1... .... .... .... .... .... width=1 dbase=1 ra=13 @xbitb_abs20_rel +CBIT_abs 0000 0000 0001 0000 0111 .... .... .... .... .... .... .... width=1 @xbit_abs24 +CBIT_rrp 0110 1010 11.. .... .... .... .... .... width=2 @xbit_disp14_rrp +CBIT_reg 0000 0000 0001 0001 0100 .... .... .... .... .... .... .... width=2 dbase=0 @xbit_disp20_reg +CBIT_reg 0110 1110 .... .... width=2 dbase=1 disp=0 @xbitw_disp0_rp +CBIT_reg 0110 1001 .... .... .... .... .... .... width=2 dbase=1 @xbitw_disp16_reg +CBIT_reg 0000 0000 0001 0001 0101 .... .... .... .... .... .... .... width=2 dbase=1 @xbit_disp20_reg +CBIT_rrp 0000 0000 0001 0001 0110 .... .... .... .... .... .... .... width=2 @xbit_disp20_rrp +CBIT_abs 0110 1111 .... .... .... .... .... .... width=2 @xbitw_abs20 +CBIT_reg 0110 1100 .... .... .... .... .... .... width=2 dbase=1 ra=12 @xbitw_abs20_rel +CBIT_reg 0110 1101 .... .... .... .... .... .... width=2 dbase=1 ra=13 @xbitw_abs20_rel +CBIT_abs 0000 0000 0001 0001 0111 .... .... .... .... .... .... .... width=2 @xbit_abs24 + +SBIT_rrp 0111 0010 10.. .... .... .... .... .... width=1 @xbit_disp14_rrp +SBIT_reg 0000 0000 0001 0000 1000 .... .... .... .... .... .... .... width=1 dbase=0 @xbit_disp20_reg +SBIT_reg 0111 0010 0... .... width=1 dbase=1 disp=0 @xbitb_disp0_rp +SBIT_reg 0111 0011 0... .... .... .... .... .... width=1 dbase=1 @xbitb_disp16_reg +SBIT_reg 0000 0000 0001 0000 1001 .... .... .... .... .... .... .... width=1 dbase=1 @xbit_disp20_reg +SBIT_rrp 0000 0000 0001 0000 1010 .... .... .... .... .... .... .... width=1 @xbit_disp20_rrp +SBIT_abs 0111 0011 1... .... .... .... .... .... width=1 @xbitb_abs20 +SBIT_reg 0111 0000 0... .... .... .... .... .... width=1 dbase=1 ra=12 @xbitb_abs20_rel +SBIT_reg 0111 0000 1... .... .... .... .... .... width=1 dbase=1 ra=13 @xbitb_abs20_rel +SBIT_abs 0000 0000 0001 0000 1011 .... .... .... .... .... .... .... width=1 @xbit_abs24 +SBIT_rrp 0111 0010 11.. .... .... .... .... .... width=2 @xbit_disp14_rrp +SBIT_reg 0000 0000 0001 0001 1000 .... .... .... .... .... .... .... width=2 dbase=0 @xbit_disp20_reg +SBIT_reg 0111 0110 .... .... width=2 dbase=1 disp=0 @xbitw_disp0_rp +SBIT_reg 0111 0001 .... .... .... .... .... .... width=2 dbase=1 @xbitw_disp16_reg +SBIT_reg 0000 0000 0001 0001 1001 .... .... .... .... .... .... .... width=2 dbase=1 @xbit_disp20_reg +SBIT_rrp 0000 0000 0001 0001 1010 .... .... .... .... .... .... .... width=2 @xbit_disp20_rrp +SBIT_abs 0111 0111 .... .... .... .... .... .... width=2 @xbitw_abs20 +SBIT_reg 0111 0100 .... .... .... .... .... .... width=2 dbase=1 ra=12 @xbitw_abs20_rel +SBIT_reg 0111 0101 .... .... .... .... .... .... width=2 dbase=1 ra=13 @xbitw_abs20_rel +SBIT_abs 0000 0000 0001 0001 1011 .... .... .... .... .... .... .... width=2 @xbit_abs24 + +TBIT_reg_imm 0000 0110 pos:4 rs:4 +TBIT_reg_reg 0000 0111 rp:4 rs:4 + +TBIT_mem_rrp 0111 1010 10.. .... .... .... .... .... width=1 @xbit_disp14_rrp +TBIT_mem_reg 0000 0000 0001 0000 1100 .... .... .... .... .... .... .... width=1 dbase=0 @xbit_disp20_reg +TBIT_mem_reg 0111 1010 0... .... width=1 dbase=1 disp=0 @xbitb_disp0_rp +TBIT_mem_reg 0111 1011 0... .... .... .... .... .... width=1 dbase=1 @xbitb_disp16_reg +TBIT_mem_reg 0000 0000 0001 0000 1101 .... .... .... .... .... .... .... width=1 dbase=1 @xbit_disp20_reg +TBIT_mem_rrp 0000 0000 0001 0000 1110 .... .... .... .... .... .... .... width=1 @xbit_disp20_rrp +TBIT_mem_abs 0111 1011 1... .... .... .... .... .... width=1 @xbitb_abs20 +TBIT_mem_reg 0111 1000 0... .... .... .... .... .... width=1 dbase=1 ra=12 @xbitb_abs20_rel +TBIT_mem_reg 0111 1000 1... .... .... .... .... .... width=1 dbase=1 ra=13 @xbitb_abs20_rel +TBIT_mem_abs 0000 0000 0001 0000 1111 .... .... .... .... .... .... .... width=1 @xbit_abs24 +TBIT_mem_rrp 0111 1010 11.. .... .... .... .... .... width=2 @xbit_disp14_rrp +TBIT_mem_reg 0000 0000 0001 0001 1100 .... .... .... .... .... .... .... width=2 dbase=0 @xbit_disp20_reg +TBIT_mem_reg 0111 1110 .... .... width=2 dbase=1 disp=0 @xbitw_disp0_rp +TBIT_mem_reg 0111 1001 .... .... .... .... .... .... width=2 dbase=1 @xbitw_disp16_reg +TBIT_mem_reg 0000 0000 0001 0001 1101 .... .... .... .... .... .... .... width=2 dbase=1 @xbit_disp20_reg +TBIT_mem_rrp 0000 0000 0001 0001 1110 .... .... .... .... .... .... .... width=2 @xbit_disp20_rrp +TBIT_mem_abs 0111 1111 .... .... .... .... .... .... width=2 @xbitw_abs20 +TBIT_mem_reg 0111 1100 .... .... .... .... .... .... width=2 dbase=1 ra=12 @xbitw_abs20_rel +TBIT_mem_reg 0111 1101 .... .... .... .... .... .... width=2 dbase=1 ra=13 @xbitw_abs20_rel +TBIT_mem_abs 0000 0000 0001 0001 1111 .... .... .... .... .... .... .... width=2 @xbit_abs24 + + ### Jumps and Linkeage ### %br_disp8 56:s4 48:4 !function=disp8_get_dest @@ -169,9 +260,6 @@ EXCP 0000 0000 1100 id:4 ### Load and Store ### -%addr_abs20 32:20 !function=reloc_abs20 -%addr_disp24 32:4 40:4 16:16 - &load rd ra dbase disp width &load_rrp rd rrp disp width &load_abs rd addr width diff --git a/target/cr16c/translate.c b/target/cr16c/translate.c index 44576dd4b4..142f0ff4b1 100644 --- a/target/cr16c/translate.c +++ b/target/cr16c/translate.c @@ -137,6 +137,33 @@ static void gen_goto(DisasContextBase *dcbase, vaddr dest, uint8_t slot) { } } +static MemOp unsigned_op_by_width[] = {0, MO_UB, MO_UW, 0, MO_UL}; + +static void gen_compute_addr_disp(TCGv_i32 dest, int ra_id, int disp, bool dbase) { + if (dbase && ra_id < CR16C_FIRST_32B_REG) { + tcg_gen_deposit_i32(dest, r[ra_id], r[ra_id+1], 16, 16); + } + else if (!dbase) { + tcg_gen_andi_i32(dest, r[ra_id], 0xFFFF); + } + else { + tcg_gen_mov_i32(dest, r[ra_id]); + } + tcg_gen_addi_i32(dest, dest, disp); +} + + +static void gen_compute_rrp_addr(TCGv_i32 dest, uint8_t rrp, uint32_t disp) { + TCGv_i32 index_reg = r[12 + rrp/8]; + uint8_t rp_id = rrp % 8; + uint8_t addr_rp_num = rp_id < 6 ? (rp_id * 2) : (3 + rp_id * 2); + + tcg_gen_deposit_i32(r[addr_rp_num], r[addr_rp_num], r[addr_rp_num + 1], 16, 16); + tcg_gen_add_i32(dest, index_reg, r[addr_rp_num]); + tcg_gen_addi_i32(dest, dest, disp); +} + + // Include generated decodetree function declarations #include "decode-insn.c.inc" @@ -1046,6 +1073,114 @@ static bool trans_LSHD_rp(DisasContext *ctx, arg_LSHD_rp *a) { } +/* Bit Operation */ + +static void gen_CBIT(TCGv_i32 addr, uint8_t pos, uint8_t width) { + uint32_t mask = ~(1 << pos); + MemOp memop = width == 2 ? MO_UW : MO_UB; + tcg_gen_atomic_and_fetch_i32(tcg_temp_new_i32(), addr, tcg_constant_i32(mask), 0, memop); +} + +static void gen_SBIT(TCGv_i32 addr, uint8_t pos, uint8_t width) { + uint32_t mask = 1 << pos; + MemOp memop = width == 2 ? MO_UW : MO_UB; + tcg_gen_atomic_or_fetch_i32(tcg_temp_new_i32(), addr, tcg_constant_i32(mask), 0, memop); +} + +static bool gen_TBIT_mem(TCGv_i32 addr, uint8_t pos, uint8_t width) { + tcg_gen_qemu_ld_i32(f_f, addr, 0, unsigned_op_by_width[width]); + tcg_gen_shri_i32(f_f, f_f, pos); + + return true; +} + + +static bool trans_CBIT_rrp(DisasContext *ctx, arg_CBIT_rrp *a) { + TCGv_i32 addr = tcg_temp_new_i32(); + + gen_compute_rrp_addr(addr, a->rrp, a->disp); + gen_CBIT(addr, a->pos, a->width); + + return true; +} + +static bool trans_CBIT_reg(DisasContext *ctx, arg_CBIT_reg *a) { + TCGv_i32 addr = tcg_temp_new_i32(); + + gen_compute_addr_disp(addr, a->ra, a->disp, a->dbase); + gen_CBIT(addr, a->pos, a->width); + + return true; +} + +static bool trans_CBIT_abs(DisasContext *ctx, arg_CBIT_abs *a) { + gen_CBIT(tcg_constant_i32(a->addr), a->pos, a->width); + + return true; +} + +static bool trans_SBIT_rrp(DisasContext *ctx, arg_SBIT_rrp *a) { + TCGv_i32 addr = tcg_temp_new_i32(); + + gen_compute_rrp_addr(addr, a->rrp, a->disp); + gen_SBIT(addr, a->pos, a->width); + + return true; +} + +static bool trans_SBIT_reg(DisasContext *ctx, arg_SBIT_reg *a) { + TCGv_i32 addr = tcg_temp_new_i32(); + + gen_compute_addr_disp(addr, a->ra, a->disp, a->dbase); + gen_SBIT(addr, a->pos, a->width); + + return true; +} + +static bool trans_SBIT_abs(DisasContext *ctx, arg_SBIT_abs *a) { + gen_SBIT(tcg_constant_i32(a->addr), a->pos, a->width); + + return true; +} + +static bool trans_TBIT_mem_rrp(DisasContext *ctx, arg_TBIT_mem_rrp *a) { + TCGv_i32 addr = tcg_temp_new_i32(); + + gen_compute_rrp_addr(addr, a->rrp, a->disp); + gen_TBIT_mem(addr, a->pos, a->width); + + return true; +} + +static bool trans_TBIT_mem_reg(DisasContext *ctx, arg_TBIT_mem_reg *a) { + TCGv_i32 addr = tcg_temp_new_i32(); + + gen_compute_addr_disp(addr, a->ra, a->disp, a->dbase); + gen_TBIT_mem(addr, a->pos, a->width); + + return true; +} + +static bool trans_TBIT_mem_abs(DisasContext *ctx, arg_TBIT_mem_abs *a) { + gen_TBIT_mem(tcg_constant_i32(a->addr), a->pos, a->width); + + return true; +} + + +static bool trans_TBIT_reg_imm(DisasContext *ctx, arg_TBIT_reg_imm *a) { + tcg_gen_shri_i32(f_f, r[a->rs], a->pos); + + return true; +} + +static bool trans_TBIT_reg_reg(DisasContext *ctx, arg_TBIT_reg_reg *a) { + tcg_gen_shr_i32(f_f, r[a->rs], r[a->rp]); + + return true; +} + + /* Jumps and Linkage */ /* For now this instruction is abused as semihosting instruction for tests */ @@ -1160,30 +1295,6 @@ static bool trans_JCOND(DisasContext* ctx, arg_JCOND *a) { /* Load and Store */ -static MemOp unsigned_op_by_width[] = {0, MO_UB, MO_UW, 0, MO_UL}; - -static void gen_compute_rrp_addr(TCGv_i32 dest, uint8_t rrp, uint32_t disp) { - TCGv_i32 index_reg = r[12 + rrp/8]; - uint8_t rp_id = rrp % 8; - uint8_t addr_rp_num = rp_id < 6 ? (rp_id * 2) : (3 + rp_id * 2); - - tcg_gen_deposit_i32(r[addr_rp_num], r[addr_rp_num], r[addr_rp_num + 1], 16, 16); - tcg_gen_add_i32(dest, index_reg, r[addr_rp_num]); - tcg_gen_addi_i32(dest, dest, disp); -} - -static void gen_compute_addr_disp(TCGv_i32 dest, int ra_id, int disp, bool dbase) { - if (dbase && ra_id < CR16C_FIRST_32B_REG) { - tcg_gen_deposit_i32(dest, r[ra_id], r[ra_id+1], 16, 16); - } - else if (!dbase) { - tcg_gen_andi_i32(dest, r[ra_id], 0xFFFF); - } - else { - tcg_gen_mov_i32(dest, r[ra_id]); - } - tcg_gen_addi_i32(dest, dest, disp); -} static void gen_move_dest(TCGv_i32 rs, int rd_id, int width) { if (width <= 2 || rd_id >= CR16C_FIRST_32B_REG) { diff --git a/tests/tcg/cr16c/test08-bitops.S b/tests/tcg/cr16c/test08-bitops.S new file mode 100644 index 0000000000..4ab2ba025f --- /dev/null +++ b/tests/tcg/cr16c/test08-bitops.S @@ -0,0 +1,432 @@ +#include "macros.inc" + +.global _start + +.text +_start: + /* Initialize registers */ + RESET + + + /*** CBIT ***/ + /*** 8 BIT ***/ + + /*** CBITB rrp disp14 ***/ + movd $0xF000, (r12) + movd $2, (r1,r0) + cbitb $1, [r12]0xFF1(r1,r0) + EXPECTM 0x0401, 0xFFF3 + RESET + + /*** CBITB reg disp20 ***/ + movw $2, r1 + cbitb $1, 0xFFF1(r1) + EXPECTM 0x0401, 0xFFF3 + RESET + + /*** CBITB rp disp0 ***/ + movd $0xFFF5, (r1,r0) + cbitb $0, 0(r1,r0) + EXPECTM 0x0604, 0xFFF5 + RESET + + /*** CBITB rp disp16 ***/ + movd $0xFFF3, (r1,r0) + cbitb $3, 0x5(r1,r0) + EXPECTM 0x0900, 0xFFF8 + RESET + + /*** CBITB rp disp20 ***/ + storb $0x08, 0x1FFF8 + storb $0x09, 0x1FFF9 + movd $0xFFF3, (r1,r0) + cbitb $3, 0x10005(r1,r0) + EXPECTM 0x0900, 0x1FFF8 + RESET + + /*** CBITB rrp disp20 ***/ + movd $1, (r12) + movd $2, (r1,r0) + cbitb $2, [r12]0xFFF1(r1,r0) + EXPECTM 0x0500, 0xFFF4 + RESET + + /*** CBITB abs20 ***/ + cbitb $1, 0xFFF7 + EXPECTM 0x0805, 0xFFF7 + RESET + + /*** CBITB abs20 rel ***/ + movd $0xFFF4, (r13) + cbitb $0, [r13]1 + EXPECTM 0x0604, 0xFFF5 + RESET + + /*** CBITB abs24 ***/ + storb $0x08, 0x10FFF8 + storb $0x09, 0x10FFF9 + cbitb $3, 0x10FFF8 + EXPECTM 0x0900, 0x10FFF8 + RESET + + /*** 16 BIT ***/ + + /*** CBITW rrp disp14 ***/ + movd $0xF000, (r12) + movd $2, (r1,r0) + cbitw $10, [r12]0xFF1(r1,r0) + EXPECTM 0x0003, 0xFFF3 + RESET + + /*** CBITW reg disp20 ***/ + movw $2, r1 + cbitw $10, 0xFFF1(r1) + EXPECTM 0x0003, 0xFFF3 + RESET + + /*** CBITW rp disp0 ***/ + movd $0xFFF5, (r1,r0) + cbitw $9, 0(r1,r0) + EXPECTM 0x0405, 0xFFF5 + RESET + + /*** CBITW rp disp16 ***/ + movd $0xFFF3, (r1,r0) + cbitw $8, 0x5(r1,r0) + EXPECTM 0x0808, 0xFFF8 + RESET + + /*** CBITW rp disp20 ***/ + storb $0x08, 0x1FFF8 + storb $0x09, 0x1FFF9 + movd $0xFFF3, (r1,r0) + cbitw $8, 0x10005(r1,r0) + EXPECTM 0x0808, 0x1FFF8 + RESET + + /*** CBITW rrp disp20 ***/ + movd $1, (r12) + movd $2, (r1,r0) + cbitw $10, [r12]0xFFF1(r1,r0) + EXPECTM 0x0104, 0xFFF4 + RESET + + /*** CBITW abs20 ***/ + cbitw $11, 0xFFF7 + EXPECTM 0x0007, 0xFFF7 + RESET + + /*** CBITW abs20 rel ***/ + movd $0xFFF4, (r13) + cbitw $9, [r13]1 + EXPECTM 0x0405, 0xFFF5 + RESET + + /*** CBITW abs24 ***/ + storb $0x08, 0x10FFF8 + storb $0x09, 0x10FFF9 + cbitw $8, 0x10FFF8 + EXPECTM 0x0808, 0x10FFF8 + RESET + + + /*** SBIT ***/ + /*** 8 BIT ***/ + + /*** SBITB rrp disp14 ***/ + movd $0xF000, (r12) + movd $2, (r1,r0) + sbitb $2, [r12]0xFF1(r1,r0) + EXPECTM 0x0407, 0xFFF3 + RESET + + /*** SBITB reg disp20 ***/ + movw $2, r1 + sbitb $2, 0xFFF1(r1) + EXPECTM 0x0407, 0xFFF3 + RESET + + /*** SBITB rp disp0 ***/ + movd $0xFFF5, (r1,r0) + sbitb $3, 0(r1,r0) + EXPECTM 0x060D, 0xFFF5 + RESET + + /*** SBITB rp disp16 ***/ + movd $0xFFF3, (r1,r0) + sbitb $1, 0x5(r1,r0) + EXPECTM 0x090A, 0xFFF8 + RESET + + /*** SBITB rp disp20 ***/ + storb $0x08, 0x1FFF8 + storb $0x09, 0x1FFF9 + movd $0xFFF3, (r1,r0) + sbitb $1, 0x10005(r1,r0) + EXPECTM 0x090A, 0x1FFF8 + RESET + + /*** SBITB rrp disp20 ***/ + movd $1, (r12) + movd $2, (r1,r0) + sbitb $0, [r12]0xFFF1(r1,r0) + EXPECTM 0x0505, 0xFFF4 + RESET + + /*** SBITB abs20 ***/ + sbitb $3, 0xFFF7 + EXPECTM 0x080F, 0xFFF7 + RESET + + /*** SBITB abs20 rel ***/ + movd $0xFFF4, (r13) + sbitb $1, [r13]1 + EXPECTM 0x0607, 0xFFF5 + RESET + + /*** SBITB abs24 ***/ + storb $0x08, 0x10FFF8 + storb $0x09, 0x10FFF9 + sbitb $2, 0x10FFF8 + EXPECTM 0x090C, 0x10FFF8 + RESET + + /*** 16 BIT ***/ + + /*** SBITW rrp disp14 ***/ + movd $0xF000, (r12) + movd $2, (r1,r0) + sbitw $9, [r12]0xFF1(r1,r0) + EXPECTM 0x0603, 0xFFF3 + RESET + + /*** SBITW reg disp20 ***/ + movw $2, r1 + sbitw $9, 0xFFF1(r1) + EXPECTM 0x0603, 0xFFF3 + RESET + + /*** SBITW rp disp0 ***/ + movd $0xFFF5, (r1,r0) + sbitw $8, 0(r1,r0) + EXPECTM 0x0705, 0xFFF5 + RESET + + /*** SBITW rp disp16 ***/ + movd $0xFFF3, (r1,r0) + sbitw $9, 0x5(r1,r0) + EXPECTM 0x0B08, 0xFFF8 + RESET + + /*** SBITW rp disp20 ***/ + storb $0x08, 0x1FFF8 + storb $0x09, 0x1FFF9 + movd $0xFFF3, (r1,r0) + sbitw $10, 0x10005(r1,r0) + EXPECTM 0x0D08, 0x1FFF8 + RESET + + /*** SBITW rrp disp20 ***/ + movd $1, (r12) + movd $2, (r1,r0) + sbitw $11, [r12]0xFFF1(r1,r0) + EXPECTM 0x0D04, 0xFFF4 + RESET + + /*** SBITW abs20 ***/ + sbitw $9, 0xFFF7 + EXPECTM 0x0A07, 0xFFF7 + RESET + + /*** SBITW abs20 rel ***/ + movd $0xFFF4, (r13) + sbitw $11, [r13]1 + EXPECTM 0x0E05, 0xFFF5 + RESET + + /*** SBITW abs24 ***/ + storb $0x08, 0x10FFF8 + storb $0x09, 0x10FFF9 + sbitw $9, 0x10FFF8 + EXPECTM 0x0B08, 0x10FFF8 + RESET + + + /*** TBIT ***/ + /*** 8 BIT ***/ + + /*** TBITB rrp disp14 ***/ + movd $0xF000, (r12) + movd $2, (r1,r0) + tbitb $1, [r12]0xFF1(r1,r0) + EXPECT_COND fs + tbitb $2, [r12]0xFF1(r1,r0) + EXPECT_COND fc + RESET + + /*** TBITB reg disp20 ***/ + movw $2, r1 + tbitb $1, 0xFFF1(r1) + EXPECT_COND fs + tbitb $2, 0xFFF1(r1) + EXPECT_COND fc + RESET + + /*** TBITB rp disp0 ***/ + movd $0xFFF5, (r1,r0) + tbitb $0, 0(r1,r0) + EXPECT_COND fs + tbitb $1, 0(r1,r0) + EXPECT_COND fc + RESET + + /*** TBITB rp disp16 ***/ + movd $0xFFF3, (r1,r0) + tbitb $2, 0x5(r1,r0) + EXPECT_COND fc + tbitb $3, 0x5(r1,r0) + EXPECT_COND fs + RESET + + /*** TBITB rp disp20 ***/ + storb $0x08, 0x1FFF8 + storb $0x09, 0x1FFF9 + movd $0xFFF3, (r1,r0) + tbitb $2, 0x10005(r1,r0) + EXPECT_COND fc + tbitb $3, 0x10005(r1,r0) + EXPECT_COND fs + RESET + + /*** TBITB rrp disp20 ***/ + movd $1, (r12) + movd $2, (r1,r0) + tbitb $2, [r12]0xFFF1(r1,r0) + EXPECT_COND fs + tbitb $3, [r12]0xFFF1(r1,r0) + EXPECT_COND fc + RESET + + /*** TBITB abs20 ***/ + tbitb $1, 0xFFF7 + EXPECT_COND fs + tbitb $3, 0xFFF7 + EXPECT_COND fc + RESET + + /*** TBITB abs20 rel ***/ + movd $0xFFF4, (r13) + tbitb $0, [r13]1 + EXPECT_COND fs + tbitb $1, [r13]1 + EXPECT_COND fc + RESET + + /*** TBITB abs24 ***/ + storb $0x08, 0x10FFF8 + storb $0x09, 0x10FFF9 + tbitb $2, 0x10FFF8 + EXPECT_COND fc + tbitb $3, 0x10FFF8 + EXPECT_COND fs + RESET + + /*** 16 BIT ***/ + + /*** TBITW rrp disp14 ***/ + movd $0xF000, (r12) + movd $2, (r1,r0) + tbitw $10, [r12]0xFF1(r1,r0) + EXPECT_COND fs + tbitw $11, [r12]0xFF1(r1,r0) + EXPECT_COND fc + RESET + + /*** TBITW reg disp20 ***/ + movw $2, r1 + tbitw $10, 0xFFF1(r1) + EXPECT_COND fs + tbitw $11, 0xFFF1(r1) + EXPECT_COND fc + RESET + + /*** TBITW rp disp0 ***/ + movd $0xFFF5, (r1,r0) + tbitw $9, 0(r1,r0) + EXPECT_COND fs + tbitw $11, 0(r1,r0) + EXPECT_COND fc + RESET + + /*** TBITW rp disp16 ***/ + movd $0xFFF3, (r1,r0) + tbitw $8, 0x5(r1,r0) + EXPECT_COND fs + tbitw $9, 0x5(r1,r0) + EXPECT_COND fc + RESET + + /*** TBITW rp disp20 ***/ + storb $0x08, 0x1FFF8 + storb $0x09, 0x1FFF9 + movd $0xFFF3, (r1,r0) + tbitw $9, 0x10005(r1,r0) + EXPECT_COND fc + tbitw $8, 0x10005(r1,r0) + EXPECT_COND fs + RESET + + /*** TBITW rrp disp20 ***/ + movd $1, (r12) + movd $2, (r1,r0) + tbitw $10, [r12]0xFFF1(r1,r0) + EXPECT_COND fs + tbitw $11, [r12]0xFFF1(r1,r0) + EXPECT_COND fc + RESET + + /*** TBITW abs20 ***/ + tbitw $11, 0xFFF7 + EXPECT_COND fs + tbitw $10, 0xFFF7 + EXPECT_COND fc + RESET + + /*** TBITW abs20 rel ***/ + movd $0xFFF4, (r13) + tbitw $9, [r13]1 + EXPECT_COND fs + tbitw $11, [r13]1 + EXPECT_COND fc + RESET + + /*** TBITW abs24 ***/ + storb $0x08, 0x10FFF8 + storb $0x09, 0x10FFF9 + tbitw $8, 0x10FFF8 + EXPECT_COND fs + tbitw $9, 0x10FFF8 + EXPECT_COND fc + RESET + + + /*** TBIT reg ***/ + + /*** TBIT cnt ***/ + tbit $1, r1 + EXPECT_COND fc + tbit $1, r2 + EXPECT_COND fs + RESET + + /*** TBIT reg ***/ + movw $1, r0 + tbit r0, r1 + EXPECT_COND fc + tbit r0, r2 + EXPECT_COND fs + RESET + + + ENDING + FAIL_HANDLER