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tests: add test for double-traps on rv64

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We do have a number of test-case for various architectures exercising
their interrupt/exception logic. However, for the recently introduced
trap API we also want to exercise the logic for double traps on at least
one architecture.

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Julian Ganz <neither@nut.email>
Message-ID: <20251027110344.2289945-31-alex.bennee@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
This commit is contained in:
Julian Ganz 2025-10-27 11:03:37 +00:00 • committed by Alex Bennée
parent 9125196aaa
commit 3c0b1fc078
2 changed files with 79 additions and 0 deletions
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6
tests/tcg/riscv64/Makefile.softmmu-target
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@ -24,5 +24,11 @@ EXTRA_RUNS += run-test-mepc-masking
run-test-mepc-masking: test-mepc-masking
$(call run-test, $<, $(QEMU) $(QEMU_OPTS)$<)
EXTRA_RUNS += run-plugin-doubletrap
run-plugin-doubletrap: doubletrap
$(call run-test, $<, \
$(QEMU) -plugin ../plugins/libdiscons.so -d plugin -D $<.pout \
$(QEMU_OPTS)$<)
# We don't currently support the multiarch system tests
undefine MULTIARCH_TESTS

73
tests/tcg/riscv64/doubletrap.S Normal file
View file

@ -0,0 +1,73 @@
.option norvc
.text
.global _start
_start:
# Set up vectored interrupts
lla t0, trap
add t0, t0, 1
csrw mtvec, t0
# Enable sw interrupts
csrrsi zero, mie, 0x8
csrrsi zero, mstatus, 0x8
# Engage the double trap: we trigger an machine-level software
# interrupt, which will trap to an illegal instruction
lui t1, 0x02000
li t0, 1
sw t0, 0(t1)
# If we still not went out via the software interrupt route after a
# short while, we failed the test.
lui t0, 0x1
0:
addi t0, t0, -1
bnez t0, 0b
j fail
trap:
j illegal_insn # Exceptions
j fail # Supervisor software interrupt
j fail
.insn i CUSTOM_0, 0, x0, x0, 0 # Machine software interrupt
j fail
j fail # Supervisor timer interrupt
j fail
j fail # Machine timer interrupt
j fail
j fail # Supervisor external interrupt
j fail
j fail # Machine external interrupt
j fail
j fail # Counter overflow interrupt
j fail
j fail
illegal_insn:
# Check whether we really got an illegal instruction
csrr t0, mcause
li t1, 2
bne t0, t1, fail
li a0, 0
j _exit
fail:
li a0, 1
_exit:
lla a1, semiargs
li t0, 0x20026 # ADP_Stopped_ApplicationExit
sd t0, 0(a1)
sd a0, 8(a1)
li a0, 0x20 # TARGET_SYS_EXIT_EXTENDED
# Semihosting call sequence
.balign 16
slli zero, zero, 0x1f
ebreak
srai zero, zero, 0x7
j .
.data
.balign 16
semiargs:
.space 16