fridtjof/qemu-cr16
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

target/riscv: Fix VSTIP bit in sstc extension.

Browse source 
VSTIP is only writable when both [mh]envcfg.STCE is enabled, or it will
revert it's defined behavior as if sstc extension is not implemented.

Signed-off-by: Jim Shu <jim.shu@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250519143518.11086-4-jim.shu@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Jim Shu 2025-05-19 22:35:17 +08:00 • committed by Alistair Francis
parent af27fc569a
commit 3cb2edae74
1 changed files with 8 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

9
target/riscv/csr.c
View file

@ -3651,7 +3651,14 @@ static RISCVException rmw_mip64(CPURISCVState *env, int csrno,
if (riscv_cpu_cfg(env)->ext_sstc && (env->priv == PRV_M) &&
get_field(env->menvcfg, MENVCFG_STCE)) {
/* sstc extension forbids STIP & VSTIP to be writeable in mip */
mask = mask & ~(MIP_STIP | MIP_VSTIP);
/* STIP is not writable when menvcfg.STCE is enabled. */
mask = mask & ~MIP_STIP;
/* VSTIP is not writable when both [mh]envcfg.STCE are enabled. */
if (get_field(env->henvcfg, HENVCFG_STCE)) {
mask = mask & ~MIP_VSTIP;
}
}
if (mask) {