wip! some correctness fixes to deal with host register storage vs actual target register size
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2badeffc2e
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42e103ca1b
1 changed files with 7 additions and 1 deletions
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@ -219,7 +219,9 @@ static void gen_compute_rrp_addr(TCGv_i32 dest, uint8_t rrp, uint32_t disp) {
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static bool trans_MOV_imm(DisasContext* ctx, arg_MOV_imm* a) {
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int len = (a->width == 4 ? 2 : a->width) * 8;
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tcg_gen_deposit_i32(r[a->rd], r[a->rd], tcg_constant_i32(a->imm), 0, len);
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//tcg_gen_deposit_i32(r[a->rd], r[a->rd], tcg_constant_i32(a->imm), 0, len);
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//tcg_gen_deposit_z_i32();
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tcg_gen_deposit_z_i32(r[a->rd], tcg_constant_i32(a->imm), 0, len);
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if (a->width == 4 && a->rd < CR16C_FIRST_32B_REG) {
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tcg_gen_movi_i32(r[a->rd + 1], a->imm >> 16);
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}
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@ -1451,6 +1453,7 @@ static bool trans_STOR(DisasContext *ctx, arg_STOR *a) {
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gen_compute_addr_disp(temp, a->ra, a->disp, a->dbase);
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gen_combine_rp(a->rs, a->width);
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tcg_gen_qemu_st_i32(r[a->rs], temp, 0, unsigned_op_by_width[a->width]);
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tcg_gen_andi_tl(r[a->rs], r[a->rs], 0xffff); /* make it 16 bits */
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return true;
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}
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@ -1461,6 +1464,7 @@ static bool trans_STOR_rrp(DisasContext *ctx, arg_STOR_rrp *a) {
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gen_compute_rrp_addr(temp, a->rrp, a->disp);
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gen_combine_rp(a->rs, a->width);
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tcg_gen_qemu_st_i32(r[a->rs], temp, 0, unsigned_op_by_width[a->width]);
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tcg_gen_andi_tl(r[a->rs], r[a->rs], 0xffff); /* make it 16 bits */
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return true;
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}
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@ -1485,6 +1489,7 @@ static bool trans_STOR_abs(DisasContext *ctx, arg_STOR_abs *a) {
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gen_combine_rp(a->rs, a->width);
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tcg_gen_qemu_st_i32(r[a->rs], tcg_constant_i32(addr), 0, unsigned_op_by_width[a->width]);
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tcg_gen_andi_tl(r[a->rs], r[a->rs], 0xffff); /* make it 16 bits */
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return true;
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}
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@ -1494,6 +1499,7 @@ static bool trans_STOR_ind_abs(DisasContext *ctx, arg_STOR_ind_abs *a) {
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tcg_gen_addi_i32(temp, r[12 + a->ri], a->addr);
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gen_combine_rp(a->rs, a->width);
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tcg_gen_qemu_st_i32(r[a->rs], temp, 0, unsigned_op_by_width[a->width]);
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tcg_gen_andi_tl(r[a->rs], r[a->rs], 0xffff); /* make it 16 bits */
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return true;
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}
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