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hw/intc: Allow gaps in hartids for aclint and aplic

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This is needed for riscv based CPUs by MIPS since those may have
sparse hart-ID layouts. ACLINT and APLIC still assume a dense
range, and if a hart is missing, this causes NULL derefs.

Signed-off-by: Chao-ying Fu <cfu@mips.com>
Signed-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20251018154522.745788-2-djordje.todorovic@htecgroup.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Djordje Todorovic 2025-10-18 15:45:28 +00:00 • committed by Alistair Francis
parent 5e3e066e4a
commit 49c24c2ae5
2 changed files with 26 additions and 5 deletions
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18
hw/intc/riscv_aclint.c
View file

@ -297,7 +297,12 @@ static void riscv_aclint_mtimer_realize(DeviceState *dev, Error **errp)
s->timecmp = g_new0(uint64_t, s->num_harts);
/* Claim timer interrupt bits */
for (i = 0; i < s->num_harts; i++) {
RISCVCPU *cpu = RISCV_CPU(cpu_by_arch_id(s->hartid_base + i));
CPUState *cpu_by_hartid = cpu_by_arch_id(s->hartid_base + i);
if (cpu_by_hartid == NULL) {
/* Valid for sparse hart layouts - skip this hart ID */
continue;
}
RISCVCPU *cpu = RISCV_CPU(cpu_by_hartid);
if (riscv_cpu_claim_interrupts(cpu, MIP_MTIP) < 0) {
error_report("MTIP already claimed");
exit(1);
@ -489,7 +494,12 @@ static void riscv_aclint_swi_realize(DeviceState *dev, Error **errp)
/* Claim software interrupt bits */
for (i = 0; i < swi->num_harts; i++) {
RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(swi->hartid_base + i));
CPUState *cpu_by_hartid = cpu_by_arch_id(swi->hartid_base + i);
if (cpu_by_hartid == NULL) {
/* Valid for sparse hart layouts - skip this hart ID */
continue;
}
RISCVCPU *cpu = RISCV_CPU(cpu_by_hartid);
/* We don't claim mip.SSIP because it is writable by software */
if (riscv_cpu_claim_interrupts(cpu, swi->sswi ? 0 : MIP_MSIP) < 0) {
error_report("MSIP already claimed");
@ -553,6 +563,10 @@ DeviceState *riscv_aclint_swi_create(hwaddr addr, uint32_t hartid_base,
for (i = 0; i < num_harts; i++) {
CPUState *cpu = cpu_by_arch_id(hartid_base + i);
if (cpu == NULL) {
/* Valid for sparse hart layouts - skip this hart ID */
continue;
}
RISCVCPU *rvcpu = RISCV_CPU(cpu);
qdev_connect_gpio_out(dev, i,

13
hw/intc/riscv_aplic.c
View file

@ -910,9 +910,12 @@ static void riscv_aplic_realize(DeviceState *dev, Error **errp)
if (!aplic->msimode) {
/* Claim the CPU interrupt to be triggered by this APLIC */
for (i = 0; i < aplic->num_harts; i++) {
RISCVCPU *cpu;
cpu = RISCV_CPU(cpu_by_arch_id(aplic->hartid_base + i));
CPUState *temp = cpu_by_arch_id(aplic->hartid_base + i);
if (temp == NULL) {
/* Valid for sparse hart layouts - skip this hart ID */
continue;
}
RISCVCPU *cpu = RISCV_CPU(temp);
if (riscv_cpu_claim_interrupts(cpu,
(aplic->mmode) ? MIP_MEIP : MIP_SEIP) < 0) {
error_report("%s already claimed",
@ -1095,6 +1098,10 @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
if (!msimode) {
for (i = 0; i < num_harts; i++) {
CPUState *cpu = cpu_by_arch_id(hartid_base + i);
if (cpu == NULL) {
/* Valid for sparse hart layouts - skip this hart ID */
continue;
}
qdev_connect_gpio_out_named(dev, NULL, i,
qdev_get_gpio_in(DEVICE(cpu),