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target/arm: Support page protections for GCS mmu indexes

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Take read and write from the s1perms.gcs bit computed
by the Arm pseudocode.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20251008215613.300150-30-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2025-10-08 14:55:29 -07:00 • committed by Peter Maydell
parent 0fe292fadb
commit 4c14265b80
1 changed files with 14 additions and 3 deletions
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17
target/arm/ptw.c
View file

@ -1619,12 +1619,16 @@ static int get_S1prot_indirect(CPUARMState *env, S1Translate *ptw,
}
}
if (perm & PAGE_WXN) {
if (regime_is_gcs(mmu_idx)) {
/*
* Note that the one s1perms.gcs bit controls both read and write
* access via AccessType_GCS. See AArch64.S1CheckPermissions.
*/
perm = (perm & PAGE_GCS ? PAGE_READ | PAGE_WRITE : 0);
} else if (perm & PAGE_WXN) {
perm &= ~PAGE_EXEC;
}
/* TODO: FEAT_GCS */
return perm & PAGE_RWX;
}
@ -2277,6 +2281,13 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
*/
prot = get_S1prot_indirect(env, ptw, mmu_idx, pi, po,
result->f.attrs.space, out_space);
} else if (regime_is_gcs(mmu_idx)) {
/*
* While one must use indirect permissions to successfully
* use GCS instructions, AArch64.S1DirectBasePermissions
* faithfully supplies s1perms.gcs = 0, Just In Case.
*/
prot = 0;
} else {
int xn = extract64(attrs, 54, 1);
int pxn = extract64(attrs, 53, 1);