CR16C: Implement cmp opcodes
This commit is contained in:
Jonas Bewig
parent
df4af6231c
commit
4d7152ee96
3 changed files with 426 additions and 35 deletions
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@ -69,8 +69,13 @@ SUBW_reg 0011 1011 .... .... @p
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### Integer Comparison
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CMPW_imm4_16 0101 0010 .... .... @param44_cmp_imm
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CMPW_reg 0101 0011 .... .... @param44_cmp
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CMPB_imm4_16 0101 0000 .... .... @param44_cmp_imm
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CMPB_reg 0101 0001 .... .... @param44_cmp
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CMPD_imm32 0000 0000 1001 .... .... .... .... .... .... .... .... .... @param4_32
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CMPD_imm4_16 0101 0110 .... .... @param44_cmp_imm
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CMPD_reg 0101 0111 .... .... @param44_cmp
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CMPW_imm4_16 0101 0010 .... .... @param44_cmp_imm
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CMPW_reg 0101 0011 .... .... @param44_cmp
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### Jumps and Linkeage
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@ -82,9 +82,12 @@ static uint64_t decode_load_bytes(DisasContext *ctx, uint64_t insn, int i, int n
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// Include generated decodetree function declarations
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#include "decode-insn.c.inc"
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static uint32_t get_imm4(DisasContext* ctx, uint8_t imm) {
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static uint16_t get_imm4(DisasContext* ctx, uint8_t imm) {
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if (imm == 11) {
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uint16_t imm_esc = cpu_lduw_code(ctx->env, ctx->base.pc_next);
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if (imm_esc << 15 == 1) {
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imm_esc = -((~imm_esc)+1);
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}
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ctx->base.pc_next += 2;
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return imm_esc;
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}
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@ -96,6 +99,13 @@ static uint32_t get_imm4(DisasContext* ctx, uint8_t imm) {
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}
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}
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static int16_t u16_to_s16(uint16_t num) {
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if ((num >> 15) == 1) {
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return -((~num)+1);
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}
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return num;
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}
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static bool trans_MOVB_imm4_16(DisasContext* ctx, arg_MOVB_imm4_16* a) {
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uint32_t imm = get_imm4(ctx, a->imm) & 0xFF;
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@ -122,7 +132,7 @@ static bool trans_MOVD_imm32(DisasContext* ctx, arg_MOVD_imm32* a) {
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}
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static bool trans_MOVD_imm4_16(DisasContext* ctx, arg_MOVD_imm4_16* a) {
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uint32_t imm = get_imm4(ctx, a->imm);
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uint32_t imm = u16_to_s16(get_imm4(ctx, a->imm));
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tcg_gen_movi_i32(r[a->rd], imm);
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tcg_gen_movi_i32(r[a->rd + 1], 0);
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@ -393,7 +403,7 @@ static bool trans_ADDD_imm32(DisasContext *ctx, arg_ADDD_imm32 *a) {
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}
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static bool trans_ADDD_imm4_16(DisasContext *ctx, arg_ADDD_imm4_16 *a) {
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uint32_t imm = get_imm4(ctx, a->imm);
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uint32_t imm = u16_to_s16(get_imm4(ctx, a->imm));
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return gen_ADDD_imm(r[a->rd], r[a->rd+1], imm);
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}
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@ -713,25 +723,88 @@ static bool trans_SUBW_reg(DisasContext *ctx, arg_SUBW_reg *a) {
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/* Integer Comparison */
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static void gen_cmp(TCGv_i32 src1, TCGv_i32 src2) {
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tcg_gen_setcond_i32(TCG_COND_EQ, f_z, src1, src2);
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tcg_gen_setcond_i32(TCG_COND_GT, f_n, src1, src2);
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tcg_gen_setcond_i32(TCG_COND_GTU, f_l, src1, src2);
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}
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static bool trans_CMPB_imm4_16(DisasContext *ctx, arg_CMPB_imm4_16 *a) {
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int32_t imm = get_imm4(ctx, a->imm) & 0xFF;
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TCGv_i32 temp = tcg_temp_new_i32();
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tcg_gen_ext8s_i32(temp, r[a->rs]);
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gen_cmp(tcg_constant_i32(imm), temp);
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return true;
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}
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static bool trans_CMPB_reg(DisasContext *ctx, arg_CMPB_reg *a) {
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TCGv_i32 temp1 = tcg_temp_new_i32();
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TCGv_i32 temp2 = tcg_temp_new_i32();
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tcg_gen_ext8s_i32(temp1, r[a->rs1]);
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tcg_gen_ext8s_i32(temp2, r[a->rs2]);
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gen_cmp(temp1, temp2);
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return true;
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}
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static bool trans_CMPD_imm4_16(DisasContext *ctx, arg_CMPD_imm4_16 *a) {
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int32_t imm = u16_to_s16(get_imm4(ctx, a->imm));
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TCGv_i32 temp_rs = tcg_temp_new_i32();
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tcg_gen_shli_i32(temp_rs, r[a->rs+1], 16);
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tcg_gen_deposit_i32(temp_rs, temp_rs, r[a->rs], 0, 16);
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gen_cmp(tcg_constant_i32(imm), temp_rs);
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return true;
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}
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static bool trans_CMPD_imm32(DisasContext *ctx, arg_CMPD_imm32 *a) {
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int32_t imm = get_imm4(ctx, a->imm);
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TCGv_i32 temp_rs = tcg_temp_new_i32();
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tcg_gen_shli_i32(temp_rs, r[a->rd+1], 16);
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tcg_gen_deposit_i32(temp_rs, temp_rs, r[a->rd], 0, 16);
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gen_cmp(tcg_constant_i32(imm), temp_rs);
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return true;
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}
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static bool trans_CMPD_reg(DisasContext *ctx, arg_CMPD_reg *a) {
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TCGv_i32 temp1 = tcg_temp_new_i32();
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TCGv_i32 temp2 = tcg_temp_new_i32();
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tcg_gen_shli_i32(temp1, r[a->rs1+1], 16);
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tcg_gen_deposit_i32(temp1, temp1, r[a->rs1], 0, 16);
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tcg_gen_shli_i32(temp2, r[a->rs2], 16);
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tcg_gen_deposit_i32(temp2, temp2, r[a->rs2], 0, 16);
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gen_cmp(temp1, temp2);
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return true;
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}
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static bool trans_CMPW_imm4_16(DisasContext *ctx, arg_CMPW_imm4_16 *a) {
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uint32_t imm = get_imm4(ctx, a->imm) & 0xFFFF;
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int32_t imm = u16_to_s16(get_imm4(ctx, a->imm));
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tcg_gen_andi_i32(r[a->rs], r[a->rs], 0xFFFF);
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tcg_gen_ext16s_i32(r[a->rs], r[a->rs]);
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tcg_gen_setcondi_i32(TCG_COND_EQ, f_z, r[a->rs], imm);
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tcg_gen_setcondi_i32(TCG_COND_LT, f_n, r[a->rs], imm);
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tcg_gen_setcondi_i32(TCG_COND_LTU, f_l, r[a->rs], imm);
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gen_cmp(tcg_constant_i32(imm), r[a->rs]);
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return true;
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}
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static bool trans_CMPW_reg(DisasContext *ctx, arg_CMPW_reg *a) {
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tcg_gen_andi_i32(r[a->rs1], r[a->rs1], 0xFFFF);
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tcg_gen_andi_i32(r[a->rs2], r[a->rs1], 0xFFFF);
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tcg_gen_ext16s_i32(r[a->rs1], r[a->rs1]);
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tcg_gen_ext16s_i32(r[a->rs2], r[a->rs2]);
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tcg_gen_setcond_i32(TCG_COND_EQ, f_z, r[a->rs1], r[a->rs2]);
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tcg_gen_setcond_i32(TCG_COND_LT, f_n, r[a->rs1], r[a->rs2]);
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tcg_gen_setcond_i32(TCG_COND_LTU, f_l, r[a->rs1], r[a->rs2]);
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gen_cmp(r[a->rs1], r[a->rs2]);
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return true;
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}
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@ -776,67 +849,67 @@ static bool trans_BRCOND_disp8(DisasContext* ctx, arg_BRCOND_disp8 *a) {
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switch (a->cond) {
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case CR16C_COND_EQ:
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tcg_gen_brcondi_i32(TCG_COND_EQ, f_z, 0, l);
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tcg_gen_brcondi_i32(TCG_COND_EQ, f_z, 1, l);
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break;
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case CR16C_COND_NE:
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tcg_gen_brcondi_i32(TCG_COND_NE, f_z, 0, l);
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tcg_gen_brcondi_i32(TCG_COND_NE, f_z, 1, l);
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break;
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case CR16C_COND_CS:
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tcg_gen_brcondi_i32(TCG_COND_EQ, f_c, 0, l);
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tcg_gen_brcondi_i32(TCG_COND_EQ, f_c, 1, l);
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break;
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case CR16C_COND_CC:
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tcg_gen_brcondi_i32(TCG_COND_NE, f_c, 0, l);
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tcg_gen_brcondi_i32(TCG_COND_NE, f_c, 1, l);
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break;
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case CR16C_COND_HI:
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tcg_gen_brcondi_i32(TCG_COND_EQ, f_l, 0, l);
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tcg_gen_brcondi_i32(TCG_COND_EQ, f_l, 1, l);
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break;
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case CR16C_COND_LS:
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tcg_gen_brcondi_i32(TCG_COND_NE, f_l, 0, l);
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tcg_gen_brcondi_i32(TCG_COND_NE, f_l, 1, l);
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break;
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case CR16C_COND_GT:
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tcg_gen_brcondi_i32(TCG_COND_EQ, f_l, 0, l);
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tcg_gen_brcondi_i32(TCG_COND_EQ, f_n, 1, l);
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break;
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case CR16C_COND_LE:
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tcg_gen_brcondi_i32(TCG_COND_NE, f_l, 0, l);
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tcg_gen_brcondi_i32(TCG_COND_NE, f_l, 1, l);
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break;
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case CR16C_COND_FS:
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tcg_gen_brcondi_i32(TCG_COND_EQ, f_f, 0, l);
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tcg_gen_brcondi_i32(TCG_COND_EQ, f_f, 1, l);
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break;
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case CR16C_COND_FC:
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tcg_gen_brcondi_i32(TCG_COND_NE, f_f, 0, l);
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tcg_gen_brcondi_i32(TCG_COND_NE, f_f, 1, l);
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break;
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case CR16C_COND_LO:
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temp = tcg_temp_new_i32();
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tcg_gen_and_i32(temp, f_z, f_l);
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tcg_gen_or_i32(temp, f_z, f_l);
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tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l);
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break;
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case CR16C_COND_HS:
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temp = tcg_temp_new_i32();
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tcg_gen_and_i32(temp, f_z, f_l);
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tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l);
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tcg_gen_brcondi_i32(TCG_COND_NE, temp, 1, l);
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break;
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case CR16C_COND_LT:
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temp = tcg_temp_new_i32();
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tcg_gen_and_i32(temp, f_z, f_l);
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tcg_gen_or_i32(temp, f_z, f_n);
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tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l);
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break;
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case CR16C_COND_GE:
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temp = tcg_temp_new_i32();
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tcg_gen_and_i32(temp, f_z, f_n);
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tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l);
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tcg_gen_brcondi_i32(TCG_COND_NE, temp, 1, l);
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break;
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}
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tcg_gen_movi_i32(f_f, 1);
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tcg_gen_movi_i32(pc, dest);
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tcg_gen_exit_tb(ctx->base.tb, 0);
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gen_set_label(l);
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tcg_gen_movi_i32(f_c, 1);
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tcg_gen_movi_i32(pc, ctx->base.pc_next);
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tcg_gen_exit_tb(ctx->base.tb, 1);
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gen_set_label(l);
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tcg_gen_movi_i32(f_f, 1);
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tcg_gen_movi_i32(pc, dest);
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tcg_gen_exit_tb(ctx->base.tb, 0);
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return true;
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}
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313
tests/tcg/cr16c/test04-cmps.S
Normal file
313
tests/tcg/cr16c/test04-cmps.S
Normal file
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@ -0,0 +1,313 @@
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#include "macros.inc"
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.global _start
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.text
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_start:
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/* Initialize registers */
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RESET
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/*** CMPB imm4/16 ***/
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/* Unsigned */
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cmpb $1, r1
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EXPECT_COND eq
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cmpb $0, r1
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EXPECT_COND ne
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cmpb $2, r1
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EXPECT_COND gt
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cmpb $0, r1
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EXPECT_COND le
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cmpb $2, r1
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EXPECT_COND hi
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cmpb $0, r1
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EXPECT_COND ls
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/* Immidiate signed */
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cmpb $-2, r1
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EXPECT_COND ls
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cmpb $-2, r1
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EXPECT_COND gt
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EXPECT 0x0A01, r1
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/* Reg signed */
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movw $0x00FF, r1
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cmpb $1, r1
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EXPECT_COND hi
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cmpb $1, r1
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EXPECT_COND le
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cmpb $-2, r1
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EXPECT_COND ls
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cmpb $-2, r1
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EXPECT_COND le
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EXPECT 0x00FF, r1
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RESET
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/*** CMPB reg ***/
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/* Unsigned */
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movw $0x2201, r2
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cmpb r2, r1
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EXPECT_COND eq
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cmpb r0, r1
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EXPECT_COND ne
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cmpb r3, r1
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EXPECT_COND gt
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cmpb r0, r1
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EXPECT_COND le
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cmpb r2, r1
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EXPECT_COND hi
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cmpb r0, r1
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EXPECT_COND ls
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EXPECT 0x0B00, r0
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EXPECT 0x0A01, r1
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EXPECT 0x2201, r2
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/* Src1 signed */
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movw $0x22FF, r2
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cmpb r2, r1
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EXPECT_COND ls
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cmpb r2, r1
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EXPECT_COND gt
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EXPECT 0x0A01, r1
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EXPECT 0x22FF, r2
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/* Src2 signed */
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cmpb r3, r2
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EXPECT_COND hi
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cmpb r3, r2
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EXPECT_COND le
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movw $0x22FE, r4
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cmpb r4, r2
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EXPECT_COND ls
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cmpb r4, r2
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EXPECT_COND le
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EXPECT 0x22FF, r2
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EXPECT 0x0803, r3
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EXPECT 0x22FE, r4
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/* Same register */
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cmpb r0, r0
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EXPECT_COND eq
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EXPECT 0x0B00, r0
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RESET
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/*** CMPD imm32 ***/
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/* Unsigned */
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cmpd $0x0A010B00, (r1,r0)
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EXPECT_COND eq
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cmpd $0, (r1,r0)
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EXPECT_COND ne
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cmpd $0x10000000, (r1,r0)
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EXPECT_COND gt
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cmpd $0x09000000, (r1,r0)
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EXPECT_COND le
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cmpd $0x10000000, (r1,r0)
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EXPECT_COND hi
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cmpd $0x09000000, (r1,r0)
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EXPECT_COND ls
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/* Immidiate signed */
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cmpd $-0x09000000, (r1,r0)
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EXPECT_COND ls
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cmpd $-0x09000000, (r1,r0)
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EXPECT_COND gt
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EXPECT 0x0B00, r0
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EXPECT 0x0A01, r1
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/* Reg signed */
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movw $-1, r0
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movw $-1, r1
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cmpd $0x10000000, (r1,r0)
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EXPECT_COND hi
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cmpd $0x10000000, (r1,r0)
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EXPECT_COND le
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cmpd $-0x09000000, (r1,r0)
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EXPECT_COND ls
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cmpd $-0x09000000, (r1,r0)
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EXPECT_COND le
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EXPECT -1, r0
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EXPECT -1, r1
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RESET
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/*** CMPD imm4/16 ***/
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/* Unsigned */
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movw $0, r5
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cmpd $0x0704, (r5,r4)
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EXPECT_COND eq
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cmpd $0, (r5,r4)
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EXPECT_COND ne
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cmpd $0x0705, (r5,r4)
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EXPECT_COND gt
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cmpd $0xEFFF, (r1,r0)
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EXPECT_COND le
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cmpd $0x0705, (r5,r4)
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EXPECT_COND hi
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cmpd $0x0703, (r5,r4)
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EXPECT_COND ls
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/* Immidiate signed */
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cmpd $-2, (r1,r0)
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EXPECT_COND ls
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cmpd $-2, (r1,r0)
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EXPECT_COND gt
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EXPECT 0x0B00, r0
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EXPECT 0x0A01, r1
|
||||
EXPECT 0x0704, r4
|
||||
EXPECT 0x0000, r5
|
||||
/* Reg signed */
|
||||
movw $-1, r0
|
||||
movw $-1, r1
|
||||
cmpd $1, (r1,r0)
|
||||
EXPECT_COND hi
|
||||
cmpd $1, (r1,r0)
|
||||
EXPECT_COND le
|
||||
cmpd $-2, (r1,r0)
|
||||
EXPECT_COND ls
|
||||
cmpd $-2, (r1,r0)
|
||||
EXPECT_COND le
|
||||
EXPECT -1, r0
|
||||
EXPECT -1, r1
|
||||
RESET
|
||||
|
||||
|
||||
/*** CMPD reg ***/
|
||||
/* Unsigned */
|
||||
movw $0x0B00, r2
|
||||
movw $0x0A01, r3
|
||||
movw $-1, r0 /* Only comparing the lower half should fail */
|
||||
cmpd (r3,r2), (r1,r0)
|
||||
EXPECT_COND eq
|
||||
cmpd (r5,r4), (r1,r0)
|
||||
EXPECT_COND ne
|
||||
cmpd (r1,r0), (r5,r4)
|
||||
EXPECT_COND gt
|
||||
cmpd (r5,r4), (r1,r0)
|
||||
EXPECT_COND le
|
||||
cmpd (r2,r1), (r4,r3)
|
||||
EXPECT_COND hi
|
||||
cmpd (r4,r3), (r2,r1)
|
||||
EXPECT_COND ls
|
||||
EXPECT -1, r0
|
||||
EXPECT 0x0A01, r1
|
||||
EXPECT 0x0B00, r2
|
||||
EXPECT 0x0A01, r3
|
||||
EXPECT 0x0704, r4
|
||||
EXPECT 0x0605, r5
|
||||
/* Src1 signed */
|
||||
movw $-1, r2
|
||||
movw $-1, r3
|
||||
cmpd (r3,r2), (r1,r0)
|
||||
EXPECT_COND ls
|
||||
cmpd (r3,r2), (r1,r0)
|
||||
EXPECT_COND gt
|
||||
EXPECT -1, r0
|
||||
EXPECT 0x0A01, r1
|
||||
EXPECT -1, r2
|
||||
EXPECT -1, r3
|
||||
/* Src2 signed */
|
||||
cmpd (r1,r0), (r3,r2)
|
||||
EXPECT_COND hi
|
||||
cmpd (r1,r0), (r3,r2)
|
||||
EXPECT_COND le
|
||||
movw $-1, r5
|
||||
movw $-2, r4
|
||||
cmpd (r5,r4), (r3,r2)
|
||||
EXPECT_COND ls
|
||||
cmpd (r5,r4), (r3,r2)
|
||||
EXPECT_COND le
|
||||
EXPECT -1, r0
|
||||
EXPECT 0x0A01, r1
|
||||
EXPECT -1, r2
|
||||
EXPECT -1, r3
|
||||
EXPECT -2, r4
|
||||
EXPECT -1, r5
|
||||
RESET
|
||||
/* Same register */
|
||||
cmpd (r1,r0), (r1,r0)
|
||||
EXPECT_COND eq
|
||||
EXPECT 0x0B00, r0
|
||||
EXPECT 0x0A01, r1
|
||||
/* Overlapping */
|
||||
cmpd (r1,r0), (r2,r1)
|
||||
EXPECT_COND gt
|
||||
EXPECT 0x0B00, r0
|
||||
EXPECT 0x0A01, r1
|
||||
EXPECT 0x0902, r2
|
||||
RESET
|
||||
|
||||
|
||||
/*** CMPW imm4/16 ***/
|
||||
/* Unsigned */
|
||||
cmpw $0x0A01, r1
|
||||
EXPECT_COND eq
|
||||
cmpw $0x0A00, r1
|
||||
EXPECT_COND ne
|
||||
cmpw $0x0A02, r1
|
||||
EXPECT_COND gt
|
||||
cmpw $0x0A00, r1
|
||||
EXPECT_COND le
|
||||
cmpw $0x0A02, r1
|
||||
EXPECT_COND hi
|
||||
cmpw $0x0A00, r1
|
||||
EXPECT_COND ls
|
||||
/* Immidiate signed */
|
||||
cmpw $-2, r1
|
||||
EXPECT_COND ls
|
||||
cmpw $-2, r1
|
||||
EXPECT_COND gt
|
||||
EXPECT 0x0A01, r1
|
||||
/* Reg signed */
|
||||
movw $-1, r1
|
||||
cmpw $1, r1
|
||||
EXPECT_COND hi
|
||||
cmpw $1, r1
|
||||
EXPECT_COND le
|
||||
cmpw $-2, r1
|
||||
EXPECT_COND ls
|
||||
cmpw $-2, r1
|
||||
EXPECT_COND le
|
||||
EXPECT -1, r1
|
||||
RESET
|
||||
|
||||
|
||||
/*** CMPW reg ***/
|
||||
/* Unsigned */
|
||||
movw $0x0A01, r2
|
||||
cmpw r2, r1
|
||||
EXPECT_COND eq
|
||||
cmpw r0, r1
|
||||
EXPECT_COND ne
|
||||
cmpw r0, r1
|
||||
EXPECT_COND gt
|
||||
cmpw r1, r0
|
||||
EXPECT_COND le
|
||||
cmpw r0, r1
|
||||
EXPECT_COND hi
|
||||
cmpw r1, r0
|
||||
EXPECT_COND ls
|
||||
EXPECT 0x0B00, r0
|
||||
EXPECT 0x0A01, r1
|
||||
EXPECT 0x0A01, r2
|
||||
/* Src1 signed */
|
||||
movw $-1, r2
|
||||
cmpw r2, r1
|
||||
EXPECT_COND ls
|
||||
cmpw r2, r1
|
||||
EXPECT_COND gt
|
||||
EXPECT 0x0A01, r1
|
||||
EXPECT -1, r2
|
||||
/* Src2 signed */
|
||||
cmpw r3, r2
|
||||
EXPECT_COND hi
|
||||
cmpw r3, r2
|
||||
EXPECT_COND le
|
||||
movw $-2, r4
|
||||
cmpw r4, r2
|
||||
EXPECT_COND ls
|
||||
cmpw r4, r2
|
||||
EXPECT_COND le
|
||||
EXPECT -1, r2
|
||||
EXPECT 0x0803, r3
|
||||
EXPECT -2, r4
|
||||
/* Same register */
|
||||
cmpw r0, r0
|
||||
EXPECT_COND eq
|
||||
EXPECT 0x0B00, r0
|
||||
RESET
|
||||
|
||||
ENDING
|
||||
FAIL_HANDLER
|
||||
Loading…
Add table
Add a link
Reference in a new issue