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* Improves s390x virtio-pci performance when using kvm

Browse source 
* Fix a problem with losing interrupts on s390x in certain cases
 * Replace legacy cpu_physical_memory_[un]map() calls in s390x code
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Merge tag 'pull-request-2025-10-10' of https://gitlab.com/thuth/qemu into staging

* Improves s390x virtio-pci performance when using kvm
* Fix a problem with losing interrupts on s390x in certain cases
* Replace legacy cpu_physical_memory_[un]map() calls in s390x code

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# gpg: Signature made Fri 10 Oct 2025 01:19:54 AM PDT
# gpg:                using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5
# gpg:                issuer "thuth@redhat.com"
# gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [unknown]
# gpg:                 aka "Thomas Huth <thuth@redhat.com>" [unknown]
# gpg:                 aka "Thomas Huth <th.huth@posteo.de>" [unknown]
# gpg:                 aka "Thomas Huth <huth@tuxfamily.org>" [unknown]
# gpg: WARNING: The key's User ID is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3  EAB9 2ED9 D774 FE70 2DB5

* tag 'pull-request-2025-10-10' of https://gitlab.com/thuth/qemu:
  s390x/pci: set kvm_msi_via_irqfd_allowed
  target/s390x: Replace legacy cpu_physical_memory_[un]map() calls (3/3)
  target/s390x: Reduce s390_store_status() scope
  target/s390x: Reduce s390_store_adtl_status() scope
  target/s390x: Replace legacy cpu_physical_memory_[un]map() calls (2/3)
  target/s390x: Propagate CPUS390XState to cpu_unmap_lowcore()
  target/s390x: Replace legacy cpu_physical_memory_[un]map() calls (1/3)
  s390x/pci: fix interrupt blocking by returning only the device's summary bit
  tests/functional: Drop the "Attempting to cache ..." log text

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2025-10-10 08:25:09 -07:00
commit 4ea22762d0
8 changed files with 164 additions and 133 deletions
Download patch file Download diff file Expand all files Collapse all files

22
hw/s390x/s390-pci-bus.c
View file

@ -652,7 +652,16 @@ static const PCIIOMMUOps s390_iommu_ops = {
.get_address_space = s390_pci_dma_iommu,
};
static uint8_t set_ind_atomic(uint64_t ind_loc, uint8_t to_be_set)
/**
* set_ind_bit_atomic - Atomically set a bit in an indicator
*
* @ind_loc: Address of the indicator
* @to_be_set: Bit to set
*
* Returns true if the bit was set by this function, false if it was
* already set or mapping failed.
*/
static bool set_ind_bit_atomic(uint64_t ind_loc, uint8_t to_be_set)
{
uint8_t expected, actual;
hwaddr len = 1;
@ -662,7 +671,7 @@ static uint8_t set_ind_atomic(uint64_t ind_loc, uint8_t to_be_set)
ind_addr = cpu_physical_memory_map(ind_loc, &len, true);
if (!ind_addr) {
s390_pci_generate_error_event(ERR_EVENT_AIRERR, 0, 0, 0, 0);
return -1;
return false;
}
actual = *ind_addr;
do {
@ -671,7 +680,7 @@ static uint8_t set_ind_atomic(uint64_t ind_loc, uint8_t to_be_set)
} while (actual != expected);
cpu_physical_memory_unmap((void *)ind_addr, len, 1, len);
return actual;
return (actual & to_be_set) ? false : true;
}
static void s390_msi_ctrl_write(void *opaque, hwaddr addr, uint64_t data,
@ -693,10 +702,10 @@ static void s390_msi_ctrl_write(void *opaque, hwaddr addr, uint64_t data,
ind_bit = pbdev->routes.adapter.ind_offset;
sum_bit = pbdev->routes.adapter.summary_offset;
set_ind_atomic(pbdev->routes.adapter.ind_addr + (ind_bit + vec) / 8,
set_ind_bit_atomic(pbdev->routes.adapter.ind_addr + (ind_bit + vec) / 8,
0x80 >> ((ind_bit + vec) % 8));
if (!set_ind_atomic(pbdev->routes.adapter.summary_addr + sum_bit / 8,
0x80 >> (sum_bit % 8))) {
if (set_ind_bit_atomic(pbdev->routes.adapter.summary_addr + sum_bit / 8,
0x80 >> (sum_bit % 8))) {
css_adapter_interrupt(CSS_IO_ADAPTER_PCI, pbdev->isc);
}
}
@ -891,6 +900,7 @@ static void s390_pcihost_realize(DeviceState *dev, Error **errp)
s390_pci_init_default_group();
css_register_io_adapters(CSS_IO_ADAPTER_PCI, true, false,
S390_ADAPTER_SUPPRESSIBLE, errp);
s390_pcihost_kvm_realize();
}
static void s390_pcihost_unrealize(DeviceState *dev)

7
include/hw/s390x/s390-pci-kvm.h
View file

@ -14,12 +14,19 @@
#include "hw/s390x/s390-pci-bus.h"
#include "hw/s390x/s390-pci-inst.h"
#include "system/kvm.h"
#ifdef CONFIG_KVM
static inline void s390_pcihost_kvm_realize(void)
{
kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled();
}
bool s390_pci_kvm_interp_allowed(void);
int s390_pci_kvm_aif_enable(S390PCIBusDevice *pbdev, ZpciFib *fib, bool assist);
int s390_pci_kvm_aif_disable(S390PCIBusDevice *pbdev);
#else
static inline void s390_pcihost_kvm_realize(void) {}
static inline bool s390_pci_kvm_interp_allowed(void)
{
return false;

122
target/s390x/helper.c
View file

@ -24,8 +24,8 @@
#include "gdbstub/helpers.h"
#include "qemu/timer.h"
#include "hw/s390x/ioinst.h"
#include "target/s390x/kvm/pv.h"
#include "system/hw_accel.h"
#include "system/memory.h"
#include "system/runstate.h"
#include "exec/target_page.h"
#include "exec/watchpoint.h"
@ -107,19 +107,23 @@ LowCore *cpu_map_lowcore(CPUS390XState *env)
{
LowCore *lowcore;
hwaddr len = sizeof(LowCore);
CPUState *cs = env_cpu(env);
const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
lowcore = cpu_physical_memory_map(env->psa, &len, true);
lowcore = address_space_map(cs->as, env->psa, &len, true, attrs);
if (len < sizeof(LowCore)) {
cpu_abort(env_cpu(env), "Could not map lowcore\n");
cpu_abort(cs, "Could not map lowcore\n");
}
return lowcore;
}
void cpu_unmap_lowcore(LowCore *lowcore)
void cpu_unmap_lowcore(CPUS390XState *env, LowCore *lowcore)
{
cpu_physical_memory_unmap(lowcore, sizeof(LowCore), 1, sizeof(LowCore));
AddressSpace *as = env_cpu(env)->as;
address_space_unmap(as, lowcore, sizeof(LowCore), true, sizeof(LowCore));
}
void do_restart_interrupt(CPUS390XState *env)
@ -134,7 +138,7 @@ void do_restart_interrupt(CPUS390XState *env)
mask = be64_to_cpu(lowcore->restart_new_psw.mask);
addr = be64_to_cpu(lowcore->restart_new_psw.addr);
cpu_unmap_lowcore(lowcore);
cpu_unmap_lowcore(env, lowcore);
env->pending_int &= ~INTERRUPT_RESTART;
s390_cpu_set_psw(env, mask, addr);
@ -177,109 +181,3 @@ void s390_cpu_recompute_watchpoints(CPUState *cs)
wp_flags, NULL);
}
}
typedef struct SigpSaveArea {
uint64_t fprs[16]; /* 0x0000 */
uint64_t grs[16]; /* 0x0080 */
PSW psw; /* 0x0100 */
uint8_t pad_0x0110[0x0118 - 0x0110]; /* 0x0110 */
uint32_t prefix; /* 0x0118 */
uint32_t fpc; /* 0x011c */
uint8_t pad_0x0120[0x0124 - 0x0120]; /* 0x0120 */
uint32_t todpr; /* 0x0124 */
uint64_t cputm; /* 0x0128 */
uint64_t ckc; /* 0x0130 */
uint8_t pad_0x0138[0x0140 - 0x0138]; /* 0x0138 */
uint32_t ars[16]; /* 0x0140 */
uint64_t crs[16]; /* 0x0384 */
} SigpSaveArea;
QEMU_BUILD_BUG_ON(sizeof(SigpSaveArea) != 512);
int s390_store_status(S390CPU *cpu, hwaddr addr, bool store_arch)
{
static const uint8_t ar_id = 1;
SigpSaveArea *sa;
hwaddr len = sizeof(*sa);
int i;
/* For PVMs storing will occur when this cpu enters SIE again */
if (s390_is_pv()) {
return 0;
}
sa = cpu_physical_memory_map(addr, &len, true);
if (!sa) {
return -EFAULT;
}
if (len != sizeof(*sa)) {
cpu_physical_memory_unmap(sa, len, 1, 0);
return -EFAULT;
}
if (store_arch) {
cpu_physical_memory_write(offsetof(LowCore, ar_access_id), &ar_id, 1);
}
for (i = 0; i < 16; ++i) {
sa->fprs[i] = cpu_to_be64(*get_freg(&cpu->env, i));
}
for (i = 0; i < 16; ++i) {
sa->grs[i] = cpu_to_be64(cpu->env.regs[i]);
}
sa->psw.addr = cpu_to_be64(cpu->env.psw.addr);
sa->psw.mask = cpu_to_be64(s390_cpu_get_psw_mask(&cpu->env));
sa->prefix = cpu_to_be32(cpu->env.psa);
sa->fpc = cpu_to_be32(cpu->env.fpc);
sa->todpr = cpu_to_be32(cpu->env.todpr);
sa->cputm = cpu_to_be64(cpu->env.cputm);
sa->ckc = cpu_to_be64(cpu->env.ckc >> 8);
for (i = 0; i < 16; ++i) {
sa->ars[i] = cpu_to_be32(cpu->env.aregs[i]);
}
for (i = 0; i < 16; ++i) {
sa->crs[i] = cpu_to_be64(cpu->env.cregs[i]);
}
cpu_physical_memory_unmap(sa, len, 1, len);
return 0;
}
typedef struct SigpAdtlSaveArea {
uint64_t vregs[32][2]; /* 0x0000 */
uint8_t pad_0x0200[0x0400 - 0x0200]; /* 0x0200 */
uint64_t gscb[4]; /* 0x0400 */
uint8_t pad_0x0420[0x1000 - 0x0420]; /* 0x0420 */
} SigpAdtlSaveArea;
QEMU_BUILD_BUG_ON(sizeof(SigpAdtlSaveArea) != 4096);
#define ADTL_GS_MIN_SIZE 2048 /* minimal size of adtl save area for GS */
int s390_store_adtl_status(S390CPU *cpu, hwaddr addr, hwaddr len)
{
SigpAdtlSaveArea *sa;
hwaddr save = len;
int i;
sa = cpu_physical_memory_map(addr, &save, true);
if (!sa) {
return -EFAULT;
}
if (save != len) {
cpu_physical_memory_unmap(sa, len, 1, 0);
return -EFAULT;
}
if (s390_has_feat(S390_FEAT_VECTOR)) {
for (i = 0; i < 32; i++) {
sa->vregs[i][0] = cpu_to_be64(cpu->env.vregs[i][0]);
sa->vregs[i][1] = cpu_to_be64(cpu->env.vregs[i][1]);
}
}
if (s390_has_feat(S390_FEAT_GUARDED_STORAGE) && len >= ADTL_GS_MIN_SIZE) {
for (i = 0; i < 4; i++) {
sa->gscb[i] = cpu_to_be64(cpu->env.gscb[i]);
}
}
cpu_physical_memory_unmap(sa, len, 1, len);
return 0;
}

5
target/s390x/s390x-internal.h
View file

@ -323,11 +323,8 @@ void s390x_cpu_timer(void *opaque);
void s390_handle_wait(S390CPU *cpu);
hwaddr s390_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
hwaddr s390_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr);
#define S390_STORE_STATUS_DEF_ADDR offsetof(LowCore, floating_pt_save_area)
int s390_store_status(S390CPU *cpu, hwaddr addr, bool store_arch);
int s390_store_adtl_status(S390CPU *cpu, hwaddr addr, hwaddr len);
LowCore *cpu_map_lowcore(CPUS390XState *env);
void cpu_unmap_lowcore(LowCore *lowcore);
void cpu_unmap_lowcore(CPUS390XState *env, LowCore *lowcore);
#endif /* CONFIG_USER_ONLY */

117
target/s390x/sigp.c
View file

@ -13,12 +13,14 @@
#include "s390x-internal.h"
#include "hw/boards.h"
#include "system/hw_accel.h"
#include "system/memory.h"
#include "system/runstate.h"
#include "system/address-spaces.h"
#include "exec/cputlb.h"
#include "system/tcg.h"
#include "trace.h"
#include "qapi/qapi-types-machine.h"
#include "target/s390x/kvm/pv.h"
QemuMutex qemu_sigp_mutex;
@ -126,6 +128,78 @@ static void sigp_stop(CPUState *cs, run_on_cpu_data arg)
si->cc = SIGP_CC_ORDER_CODE_ACCEPTED;
}
typedef struct SigpSaveArea {
uint64_t fprs[16]; /* 0x0000 */
uint64_t grs[16]; /* 0x0080 */
PSW psw; /* 0x0100 */
uint8_t pad_0x0110[0x0118 - 0x0110]; /* 0x0110 */
uint32_t prefix; /* 0x0118 */
uint32_t fpc; /* 0x011c */
uint8_t pad_0x0120[0x0124 - 0x0120]; /* 0x0120 */
uint32_t todpr; /* 0x0124 */
uint64_t cputm; /* 0x0128 */
uint64_t ckc; /* 0x0130 */
uint8_t pad_0x0138[0x0140 - 0x0138]; /* 0x0138 */
uint32_t ars[16]; /* 0x0140 */
uint64_t crs[16]; /* 0x0384 */
} SigpSaveArea;
QEMU_BUILD_BUG_ON(sizeof(SigpSaveArea) != 512);
#define S390_STORE_STATUS_DEF_ADDR offsetof(LowCore, floating_pt_save_area)
static int s390_store_status(S390CPU *cpu, hwaddr addr, bool store_arch)
{
const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
AddressSpace *as = CPU(cpu)->as;
SigpSaveArea *sa;
hwaddr len = sizeof(*sa);
int i;
/* For PVMs storing will occur when this cpu enters SIE again */
if (s390_is_pv()) {
return 0;
}
sa = address_space_map(as, addr, &len, true, attrs);
if (!sa) {
return -EFAULT;
}
if (len != sizeof(*sa)) {
address_space_unmap(as, sa, len, true, 0);
return -EFAULT;
}
if (store_arch) {
static const uint8_t ar_id = 1;
address_space_stb(as, offsetof(LowCore, ar_access_id),
ar_id, attrs, NULL);
}
for (i = 0; i < 16; ++i) {
sa->fprs[i] = cpu_to_be64(*get_freg(&cpu->env, i));
}
for (i = 0; i < 16; ++i) {
sa->grs[i] = cpu_to_be64(cpu->env.regs[i]);
}
sa->psw.addr = cpu_to_be64(cpu->env.psw.addr);
sa->psw.mask = cpu_to_be64(s390_cpu_get_psw_mask(&cpu->env));
sa->prefix = cpu_to_be32(cpu->env.psa);
sa->fpc = cpu_to_be32(cpu->env.fpc);
sa->todpr = cpu_to_be32(cpu->env.todpr);
sa->cputm = cpu_to_be64(cpu->env.cputm);
sa->ckc = cpu_to_be64(cpu->env.ckc >> 8);
for (i = 0; i < 16; ++i) {
sa->ars[i] = cpu_to_be32(cpu->env.aregs[i]);
}
for (i = 0; i < 16; ++i) {
sa->crs[i] = cpu_to_be64(cpu->env.cregs[i]);
}
address_space_unmap(as, sa, len, true, len);
return 0;
}
static void sigp_stop_and_store_status(CPUState *cs, run_on_cpu_data arg)
{
S390CPU *cpu = S390_CPU(cs);
@ -172,6 +246,49 @@ static void sigp_store_status_at_address(CPUState *cs, run_on_cpu_data arg)
si->cc = SIGP_CC_ORDER_CODE_ACCEPTED;
}
typedef struct SigpAdtlSaveArea {
uint64_t vregs[32][2]; /* 0x0000 */
uint8_t pad_0x0200[0x0400 - 0x0200]; /* 0x0200 */
uint64_t gscb[4]; /* 0x0400 */
uint8_t pad_0x0420[0x1000 - 0x0420]; /* 0x0420 */
} SigpAdtlSaveArea;
QEMU_BUILD_BUG_ON(sizeof(SigpAdtlSaveArea) != 4096);
#define ADTL_GS_MIN_SIZE 2048 /* minimal size of adtl save area for GS */
static int s390_store_adtl_status(S390CPU *cpu, hwaddr addr, hwaddr len)
{
const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
AddressSpace *as = CPU(cpu)->as;
SigpAdtlSaveArea *sa;
hwaddr save = len;
int i;
sa = address_space_map(as, addr, &save, true, attrs);
if (!sa) {
return -EFAULT;
}
if (save != len) {
address_space_unmap(as, sa, len, true, 0);
return -EFAULT;
}
if (s390_has_feat(S390_FEAT_VECTOR)) {
for (i = 0; i < 32; i++) {
sa->vregs[i][0] = cpu_to_be64(cpu->env.vregs[i][0]);
sa->vregs[i][1] = cpu_to_be64(cpu->env.vregs[i][1]);
}
}
if (s390_has_feat(S390_FEAT_GUARDED_STORAGE) && len >= ADTL_GS_MIN_SIZE) {
for (i = 0; i < 4; i++) {
sa->gscb[i] = cpu_to_be64(cpu->env.gscb[i]);
}
}
address_space_unmap(as, sa, len, true, len);
return 0;
}
#define ADTL_SAVE_LC_MASK 0xfUL
static void sigp_store_adtl_status(CPUState *cs, run_on_cpu_data arg)
{

19
target/s390x/tcg/excp_helper.c
View file

@ -30,6 +30,7 @@
#ifndef CONFIG_USER_ONLY
#include "qemu/timer.h"
#include "system/address-spaces.h"
#include "system/memory.h"
#include "hw/s390x/ioinst.h"
#include "hw/s390x/s390_flic.h"
#include "hw/boards.h"
@ -284,7 +285,7 @@ static void do_program_interrupt(CPUS390XState *env)
addr = be64_to_cpu(lowcore->program_new_psw.addr);
lowcore->per_breaking_event_addr = cpu_to_be64(env->gbea);
cpu_unmap_lowcore(lowcore);
cpu_unmap_lowcore(env, lowcore);
s390_cpu_set_psw(env, mask, addr);
}
@ -303,7 +304,7 @@ static void do_svc_interrupt(CPUS390XState *env)
mask = be64_to_cpu(lowcore->svc_new_psw.mask);
addr = be64_to_cpu(lowcore->svc_new_psw.addr);
cpu_unmap_lowcore(lowcore);
cpu_unmap_lowcore(env, lowcore);
s390_cpu_set_psw(env, mask, addr);
@ -377,7 +378,7 @@ static void do_ext_interrupt(CPUS390XState *env)
lowcore->external_old_psw.mask = cpu_to_be64(s390_cpu_get_psw_mask(env));
lowcore->external_old_psw.addr = cpu_to_be64(env->psw.addr);
cpu_unmap_lowcore(lowcore);
cpu_unmap_lowcore(env, lowcore);
s390_cpu_set_psw(env, mask, addr);
}
@ -404,7 +405,7 @@ static void do_io_interrupt(CPUS390XState *env)
mask = be64_to_cpu(lowcore->io_new_psw.mask);
addr = be64_to_cpu(lowcore->io_new_psw.addr);
cpu_unmap_lowcore(lowcore);
cpu_unmap_lowcore(env, lowcore);
g_free(io);
s390_cpu_set_psw(env, mask, addr);
@ -418,16 +419,18 @@ QEMU_BUILD_BUG_ON(sizeof(MchkExtSaveArea) != 1024);
static int mchk_store_vregs(CPUS390XState *env, uint64_t mcesao)
{
const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
AddressSpace *as = env_cpu(env)->as;
hwaddr len = sizeof(MchkExtSaveArea);
MchkExtSaveArea *sa;
int i;
sa = cpu_physical_memory_map(mcesao, &len, true);
sa = address_space_map(as, mcesao, &len, true, attrs);
if (!sa) {
return -EFAULT;
}
if (len != sizeof(MchkExtSaveArea)) {
cpu_physical_memory_unmap(sa, len, 1, 0);
address_space_unmap(as, sa, len, true, 0);
return -EFAULT;
}
@ -436,7 +439,7 @@ static int mchk_store_vregs(CPUS390XState *env, uint64_t mcesao)
sa->vregs[i][1] = cpu_to_be64(env->vregs[i][1]);
}
cpu_physical_memory_unmap(sa, len, 1, len);
address_space_unmap(as, sa, len, true, len);
return 0;
}
@ -488,7 +491,7 @@ static void do_mchk_interrupt(CPUS390XState *env)
mask = be64_to_cpu(lowcore->mcck_new_psw.mask);
addr = be64_to_cpu(lowcore->mcck_new_psw.addr);
cpu_unmap_lowcore(lowcore);
cpu_unmap_lowcore(env, lowcore);
s390_cpu_set_psw(env, mask, addr);
}

4
target/s390x/tcg/misc_helper.c
View file

@ -570,7 +570,7 @@ uint32_t HELPER(tpi)(CPUS390XState *env, uint64_t addr)
lowcore->subchannel_nr = cpu_to_be16(io->nr);
lowcore->io_int_parm = cpu_to_be32(io->parm);
lowcore->io_int_word = cpu_to_be32(io->word);
cpu_unmap_lowcore(lowcore);
cpu_unmap_lowcore(env, lowcore);
}
g_free(io);
@ -700,7 +700,7 @@ void HELPER(stfl)(CPUS390XState *env)
lowcore = cpu_map_lowcore(env);
prepare_stfl();
memcpy(&lowcore->stfl_fac_list, stfl_bytes, sizeof(lowcore->stfl_fac_list));
cpu_unmap_lowcore(lowcore);
cpu_unmap_lowcore(env, lowcore);
}
#endif

1
tests/functional/qemu_test/asset.py
View file

@ -225,7 +225,6 @@ class Asset:
log.addHandler(handler)
for name, asset in vars(test.__class__).items():
if name.startswith("ASSET_") and type(asset) == Asset:
log.info("Attempting to cache '%s'" % asset)
try:
asset.fetch()
except AssetError as e: