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target/arm: Implement BFMLSLB{L, T} for SME2/SVE2p1

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250704142112.1018902-87-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2025-07-04 08:20:49 -06:00 • committed by Peter Maydell
parent 1de7ecfc12
commit 4fddbdf934
2 changed files with 36 additions and 0 deletions
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6
target/arm/tcg/sve.decode
View file

@ -1727,18 +1727,24 @@ FMLSLT_zzzw 01100100 10 1 ..... 10 1 00 1 ..... ..... @rda_rn_rm_ex esz=2
BFMLALB_zzzw 01100100 11 1 ..... 10 0 00 0 ..... ..... @rda_rn_rm_ex esz=2
BFMLALT_zzzw 01100100 11 1 ..... 10 0 00 1 ..... ..... @rda_rn_rm_ex esz=2
BFMLSLB_zzzw 01100100 11 1 ..... 10 1 00 0 ..... ..... @rda_rn_rm_ex esz=2
BFMLSLT_zzzw 01100100 11 1 ..... 10 1 00 1 ..... ..... @rda_rn_rm_ex esz=2
### SVE2 floating-point dot-product
FDOT_zzzz 01100100 00 1 ..... 10 0 00 0 ..... ..... @rda_rn_rm_ex esz=2
BFDOT_zzzz 01100100 01 1 ..... 10 0 00 0 ..... ..... @rda_rn_rm_ex esz=2
### SVE2 floating-point multiply-add long (indexed)
FMLALB_zzxw 01100100 10 1 ..... 0100.0 ..... ..... @rrxr_3a esz=2
FMLALT_zzxw 01100100 10 1 ..... 0100.1 ..... ..... @rrxr_3a esz=2
FMLSLB_zzxw 01100100 10 1 ..... 0110.0 ..... ..... @rrxr_3a esz=2
FMLSLT_zzxw 01100100 10 1 ..... 0110.1 ..... ..... @rrxr_3a esz=2
BFMLALB_zzxw 01100100 11 1 ..... 0100.0 ..... ..... @rrxr_3a esz=2
BFMLALT_zzxw 01100100 11 1 ..... 0100.1 ..... ..... @rrxr_3a esz=2
BFMLSLB_zzxw 01100100 11 1 ..... 0110.0 ..... ..... @rrxr_3a esz=2
BFMLSLT_zzxw 01100100 11 1 ..... 0110.1 ..... ..... @rrxr_3a esz=2
### SVE2 floating-point dot-product (indexed)

30
target/arm/tcg/translate-sve.c
View file

@ -7421,6 +7421,36 @@ static bool do_BFMLAL_zzxw(DisasContext *s, arg_rrxr_esz *a, bool sel)
TRANS_FEAT(BFMLALB_zzxw, aa64_sve_bf16, do_BFMLAL_zzxw, a, false)
TRANS_FEAT(BFMLALT_zzxw, aa64_sve_bf16, do_BFMLAL_zzxw, a, true)
static bool do_BFMLSL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel)
{
if (s->fpcr_ah) {
return gen_gvec_fpst_zzzz(s, gen_helper_gvec_ah_bfmlsl,
a->rd, a->rn, a->rm, a->ra, sel, FPST_AH);
} else {
return gen_gvec_fpst_zzzz(s, gen_helper_gvec_bfmlsl,
a->rd, a->rn, a->rm, a->ra, sel, FPST_A64);
}
}
TRANS_FEAT(BFMLSLB_zzzw, aa64_sme2_or_sve2p1, do_BFMLSL_zzzw, a, false)
TRANS_FEAT(BFMLSLT_zzzw, aa64_sme2_or_sve2p1, do_BFMLSL_zzzw, a, true)
static bool do_BFMLSL_zzxw(DisasContext *s, arg_rrxr_esz *a, bool sel)
{
if (s->fpcr_ah) {
return gen_gvec_fpst_zzzz(s, gen_helper_gvec_ah_bfmlsl_idx,
a->rd, a->rn, a->rm, a->ra,
(a->index << 1) | sel, FPST_AH);
} else {
return gen_gvec_fpst_zzzz(s, gen_helper_gvec_bfmlsl_idx,
a->rd, a->rn, a->rm, a->ra,
(a->index << 1) | sel, FPST_A64);
}
}
TRANS_FEAT(BFMLSLB_zzxw, aa64_sme2_or_sve2p1, do_BFMLSL_zzxw, a, false)
TRANS_FEAT(BFMLSLT_zzxw, aa64_sme2_or_sve2p1, do_BFMLSL_zzxw, a, true)
static bool trans_PSEL(DisasContext *s, arg_psel *a)
{
int vl = vec_full_reg_size(s);