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target/openrisc: Inline tcg_gen_trunc_i64_tl()

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The OpenRISC targets are only built as 32-bit, so tcg_gen_trunc_i64_tl
expands to tcg_gen_extrl_i64_i32(). Use the latter to simplify the
next commit mechanical change.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20251010070702.51484-13-philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2025-10-08 09:32:05 +02:00
parent 4f6c60683f
commit 500708331e
1 changed files with 3 additions and 3 deletions
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6
target/openrisc/translate.c
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@ -351,7 +351,7 @@ static void gen_macu(DisasContext *dc, TCGv srca, TCGv srcb)
/* Note that overflow is only computed during addition stage. */
tcg_gen_add_i64(cpu_mac, cpu_mac, t1);
tcg_gen_setcond_i64(TCG_COND_LTU, t1, cpu_mac, t1);
tcg_gen_trunc_i64_tl(cpu_sr_cy, t1);
tcg_gen_extrl_i64_i32(cpu_sr_cy, t1);
gen_ove_cy(dc);
}
@ -392,7 +392,7 @@ static void gen_msbu(DisasContext *dc, TCGv srca, TCGv srcb)
/* Note that overflow is only computed during subtraction stage. */
tcg_gen_setcond_i64(TCG_COND_LTU, t2, cpu_mac, t1);
tcg_gen_sub_i64(cpu_mac, cpu_mac, t1);
tcg_gen_trunc_i64_tl(cpu_sr_cy, t2);
tcg_gen_extrl_i64_i32(cpu_sr_cy, t2);
gen_ove_cy(dc);
}
@ -917,7 +917,7 @@ static bool trans_l_movhi(DisasContext *dc, arg_l_movhi *a)
static bool trans_l_macrc(DisasContext *dc, arg_l_macrc *a)
{
check_r0_write(dc, a->d);
tcg_gen_trunc_i64_tl(cpu_R(dc, a->d), cpu_mac);
tcg_gen_extrl_i64_i32(cpu_R(dc, a->d), cpu_mac);
tcg_gen_movi_i64(cpu_mac, 0);
return true;
}