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hw/arm/aspeed: Fix missing SPI IRQ connection causing DMA interrupt failure

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It did not connect SPI IRQ to the Interrupt Controller, so even the SPI
model raised the IRQ, the interrupt was not received. The CPU therefore
did not trigger an interrupt via the controller, and the firmware never
received the interrupt.

Fixes: 356b230ed1 ("aspeed/soc: Add AST1030 support")
Fixes: f25c0ae107 ("aspeed/soc: Add AST2600 support")
Fixes: 5dd883ab06 ("aspeed/soc: Add AST2700 support")
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20251106084925.1253704-2-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
This commit is contained in:
Jamin Lin 2025-11-06 16:49:10 +08:00 • committed by Cédric Le Goater
parent cacd8fb08d
commit 510d5c61ad
3 changed files with 6 additions and 0 deletions
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2
hw/arm/aspeed_ast10x0.c
View file

@ -372,6 +372,8 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
sc->memmap[ASPEED_DEV_SPI1 + i]);
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->spi[i]), 1,
ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
aspeed_soc_ast1030_get_irq(s, ASPEED_DEV_SPI1 + i));
}
/* Secure Boot Controller */

2
hw/arm/aspeed_ast2600.c
View file

@ -557,6 +557,8 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
sc->memmap[ASPEED_DEV_SPI1 + i]);
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->spi[i]), 1,
ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
aspeed_soc_ast2600_get_irq(s, ASPEED_DEV_SPI1 + i));
}
/* EHCI */

2
hw/arm/aspeed_ast27x0.c
View file

@ -831,6 +831,8 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
sc->memmap[ASPEED_DEV_SPI0 + i]);
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->spi[i]), 1,
ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_SPI0 + i));
}
/* EHCI */