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hw/arm/xlnx-versal: adma: refactor creation

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Refactor the ADMA creation using the VersalMap structure.

Note that the connection to the CRL is removed for now and will be
re-added by next commits.

Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20250926070806.292065-8-luc.michel@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Luc Michel 2025-09-26 09:07:25 +02:00 • committed by Peter Maydell
parent 8aaeb96405
commit 51668b79be
3 changed files with 48 additions and 54 deletions
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28
hw/arm/xlnx-versal-virt.c
View file

@ -204,33 +204,6 @@ static void fdt_add_usb_xhci_nodes(VersalVirt *s)
g_free(name);
}
static void fdt_add_zdma_nodes(VersalVirt *s)
{
const char clocknames[] = "clk_main\0clk_apb";
const char compat[] = "xlnx,zynqmp-dma-1.0";
int i;
for (i = XLNX_VERSAL_NR_ADMAS - 1; i >= 0; i--) {
uint64_t addr = MM_ADMA_CH0 + MM_ADMA_CH0_SIZE * i;
char *name = g_strdup_printf("/dma@%" PRIx64, addr);
qemu_fdt_add_subnode(s->fdt, name);
qemu_fdt_setprop_cell(s->fdt, name, "xlnx,bus-width", 64);
qemu_fdt_setprop_cells(s->fdt, name, "clocks",
s->phandle.clk_25Mhz, s->phandle.clk_25Mhz);
qemu_fdt_setprop(s->fdt, name, "clock-names",
clocknames, sizeof(clocknames));
qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
GIC_FDT_IRQ_TYPE_SPI, VERSAL_ADMA_IRQ_0 + i,
GIC_FDT_IRQ_FLAGS_LEVEL_HI);
qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
2, addr, 2, 0x1000);
qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat));
g_free(name);
}
}
static void fdt_add_rtc_node(VersalVirt *s)
{
const char compat[] = "xlnx,zynqmp-rtc";
@ -561,7 +534,6 @@ static void versal_virt_init(MachineState *machine)
fdt_add_gic_nodes(s);
fdt_add_timer_nodes(s);
fdt_add_zdma_nodes(s);
fdt_add_usb_xhci_nodes(s);
fdt_add_rtc_node(s);
fdt_add_bbram_node(s);

72
hw/arm/xlnx-versal.c
View file

@ -30,6 +30,7 @@
#include "hw/net/xlnx-versal-canfd.h"
#include "hw/sd/sdhci.h"
#include "hw/net/cadence_gem.h"
#include "hw/dma/xlnx-zdma.h"
#define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72")
#define XLNX_VERSAL_RCPU_TYPE ARM_CPU_TYPE_NAME("cortex-r5f")
@ -60,6 +61,16 @@ typedef struct VersalMap {
const uint32_t speed;
} gem[3];
size_t num_gem;
struct VersalZDMAMap {
const char *name;
VersalSimplePeriphMap map;
size_t num_chan;
uint64_t chan_stride;
int irq_stride;
} zdma[2];
size_t num_zdma;
} VersalMap;
static const VersalMap VERSAL_MAP = {
@ -78,6 +89,9 @@ static const VersalMap VERSAL_MAP = {
.gem[0] = { { 0xff0c0000, 56 }, 2, "rgmii-id", 1000 },
.gem[1] = { { 0xff0d0000, 58 }, 2, "rgmii-id", 1000 },
.num_gem = 2,
.zdma[0] = { "adma", { 0xffa80000, 60 }, 8, 0x10000, 1 },
.num_zdma = 1,
};
static const VersalMap *VERSION_TO_MAP[] = {
@ -492,30 +506,45 @@ static void versal_create_gem_fdt(Versal *s,
sizeof(uint32_t) * map->num_prio_queue * 3);
}
static void versal_create_admas(Versal *s, qemu_irq *pic)
static void versal_create_zdma(Versal *s,
const struct VersalZDMAMap *map)
{
int i;
DeviceState *dev;
MemoryRegion *mr;
g_autofree char *name;
const char compatible[] = "xlnx,zynqmp-dma-1.0";
const char clocknames[] = "clk_main\0clk_apb";
size_t i;
for (i = 0; i < ARRAY_SIZE(s->lpd.iou.adma); i++) {
char *name = g_strdup_printf("adma%d", i);
DeviceState *dev;
MemoryRegion *mr;
name = g_strdup_printf("%s[*]", map->name);
object_initialize_child(OBJECT(s), name, &s->lpd.iou.adma[i],
TYPE_XLNX_ZDMA);
dev = DEVICE(&s->lpd.iou.adma[i]);
for (i = 0; i < map->num_chan; i++) {
uint64_t addr = map->map.addr + map->chan_stride * i;
int irq = map->map.irq + map->irq_stride * i;
g_autofree char *node;
dev = qdev_new(TYPE_XLNX_ZDMA);
object_property_add_child(OBJECT(s), name, OBJECT(dev));
object_property_set_int(OBJECT(dev), "bus-width", 128, &error_abort);
object_property_set_link(OBJECT(dev), "dma",
OBJECT(get_system_memory()), &error_fatal);
sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
memory_region_add_subregion(&s->mr_ps,
MM_ADMA_CH0 + i * MM_ADMA_CH0_SIZE, mr);
memory_region_add_subregion(&s->mr_ps, addr, mr);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[VERSAL_ADMA_IRQ_0 + i]);
g_free(name);
versal_sysbus_connect_irq(s, SYS_BUS_DEVICE(dev), 0, irq);
node = versal_fdt_add_simple_subnode(s, "/dma", addr, 0x1000,
compatible, sizeof(compatible));
qemu_fdt_setprop_cell(s->cfg.fdt, node, "xlnx,bus-width", 64);
qemu_fdt_setprop_cells(s->cfg.fdt, node, "clocks",
s->phandle.clk_25mhz, s->phandle.clk_25mhz);
qemu_fdt_setprop(s->cfg.fdt, node, "clock-names",
clocknames, sizeof(clocknames));
qemu_fdt_setprop_cells(s->cfg.fdt, node, "interrupts",
GIC_FDT_IRQ_TYPE_SPI, irq,
GIC_FDT_IRQ_FLAGS_LEVEL_HI);
}
}
@ -978,14 +1007,6 @@ static void versal_create_crl(Versal *s, qemu_irq *pic)
&error_abort);
}
for (i = 0; i < ARRAY_SIZE(s->lpd.iou.adma); i++) {
g_autofree gchar *name = g_strdup_printf("adma[%d]", i);
object_property_set_link(OBJECT(&s->lpd.crl),
name, OBJECT(&s->lpd.iou.adma[i]),
&error_abort);
}
object_property_set_link(OBJECT(&s->lpd.crl),
"usb", OBJECT(&s->lpd.iou.usb),
&error_abort);
@ -1171,8 +1192,11 @@ static void versal_realize(DeviceState *dev, Error **errp)
versal_create_gem_fdt(s, &map->gem[map->num_gem - 1 - i]);
}
for (i = 0; i < map->num_zdma; i++) {
versal_create_zdma(s, &map->zdma[i]);
}
versal_create_usbs(s, pic);
versal_create_admas(s, pic);
versal_create_pmc_apb_irq_orgate(s, pic);
versal_create_rtc(s, pic);
versal_create_trng(s, pic);

2
include/hw/arm/xlnx-versal.h
View file

@ -17,7 +17,6 @@
#include "hw/cpu/cluster.h"
#include "hw/or-irq.h"
#include "hw/intc/arm_gicv3.h"
#include "hw/dma/xlnx-zdma.h"
#include "hw/rtc/xlnx-zynqmp-rtc.h"
#include "qom/object.h"
#include "hw/usb/xlnx-usb-subsystem.h"
@ -77,7 +76,6 @@ struct Versal {
MemoryRegion mr_ocm;
struct {
XlnxZDMA adma[XLNX_VERSAL_NR_ADMAS];
VersalUsb2 usb;
} iou;