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MAX78000: Add MAX78000FTHR Machine

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This patch adds support for the MAX78000FTHR machine.

The MAX78000FTHR contains a MAX78000 and a RISC-V core. This patch
implements only the MAX78000, which is Cortex-M4 based.
Details can be found at:
https://www.analog.com/media/en/technical-documentation/user-guides/max78000-user-guide.pdf

Signed-off-by: Jackson Donaldson <jcksn@duck.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20250704223239.248781-2-jcksn@duck.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Jackson Donaldson 2025-07-04 18:32:29 -04:00 • committed by Peter Maydell
parent df6fe2abf2
commit 51eb283dd0
5 changed files with 269 additions and 0 deletions
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10
hw/arm/Kconfig
View file

@ -95,6 +95,12 @@ config INTEGRATOR
select PL181 # display select PL181 # display
select SMC91C111 select SMC91C111
config MAX78000FTHR
bool
default y
depends on TCG && ARM
select MAX78000_SOC
config MPS3R config MPS3R
bool bool
default y default y
@ -357,6 +363,10 @@ config ALLWINNER_R40
select USB_EHCI_SYSBUS select USB_EHCI_SYSBUS
select SD select SD
config MAX78000_SOC
bool
select ARM_V7M
config RASPI config RASPI
bool bool
default y default y

172
hw/arm/max78000_soc.c Normal file
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@ -0,0 +1,172 @@
/*
* MAX78000 SOC
*
* Copyright (c) 2025 Jackson Donaldson <jcksn@duck.com>
*
* SPDX-License-Identifier: GPL-2.0-or-later
*
* Implementation based on stm32f205 and Max78000 user guide at
* https://www.analog.com/media/en/technical-documentation/user-guides/max78000-user-guide.pdf
*/
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "system/address-spaces.h"
#include "system/system.h"
#include "hw/arm/max78000_soc.h"
#include "hw/qdev-clock.h"
#include "hw/misc/unimp.h"
static void max78000_soc_initfn(Object *obj)
{
MAX78000State *s = MAX78000_SOC(obj);
object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
}
static void max78000_soc_realize(DeviceState *dev_soc, Error **errp)
{
MAX78000State *s = MAX78000_SOC(dev_soc);
MemoryRegion *system_memory = get_system_memory();
DeviceState *armv7m;
Error *err = NULL;
if (!clock_has_source(s->sysclk)) {
error_setg(errp, "sysclk clock must be wired up by the board code");
return;
}
memory_region_init_rom(&s->flash, OBJECT(dev_soc), "MAX78000.flash",
FLASH_SIZE, &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, &s->flash);
memory_region_init_ram(&s->sram, NULL, "MAX78000.sram", SRAM_SIZE,
&err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram);
armv7m = DEVICE(&s->armv7m);
/*
* The MAX78000 user guide's Interrupt Vector Table section
* suggests that there are 120 IRQs in the text, while only listing
* 104 in table 5-1. Implement the more generous of the two.
* This has not been tested in hardware.
*/
qdev_prop_set_uint32(armv7m, "num-irq", 120);
qdev_prop_set_uint8(armv7m, "num-prio-bits", 3);
qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"));
qdev_prop_set_bit(armv7m, "enable-bitband", true);
qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
object_property_set_link(OBJECT(&s->armv7m), "memory",
OBJECT(system_memory), &error_abort);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) {
return;
}
create_unimplemented_device("globalControl", 0x40000000, 0x400);
create_unimplemented_device("systemInterface", 0x40000400, 0x400);
create_unimplemented_device("functionControl", 0x40000800, 0x400);
create_unimplemented_device("watchdogTimer0", 0x40003000, 0x400);
create_unimplemented_device("dynamicVoltScale", 0x40003c00, 0x40);
create_unimplemented_device("SIMO", 0x40004400, 0x400);
create_unimplemented_device("trimSystemInit", 0x40005400, 0x400);
create_unimplemented_device("generalCtrlFunc", 0x40005800, 0x400);
create_unimplemented_device("wakeupTimer", 0x40006400, 0x400);
create_unimplemented_device("powerSequencer", 0x40006800, 0x400);
create_unimplemented_device("miscControl", 0x40006c00, 0x400);
create_unimplemented_device("aes", 0x40007400, 0x400);
create_unimplemented_device("aesKey", 0x40007800, 0x400);
create_unimplemented_device("gpio0", 0x40008000, 0x1000);
create_unimplemented_device("gpio1", 0x40009000, 0x1000);
create_unimplemented_device("parallelCamInterface", 0x4000e000, 0x1000);
create_unimplemented_device("CRC", 0x4000f000, 0x1000);
create_unimplemented_device("timer0", 0x40010000, 0x1000);
create_unimplemented_device("timer1", 0x40011000, 0x1000);
create_unimplemented_device("timer2", 0x40012000, 0x1000);
create_unimplemented_device("timer3", 0x40013000, 0x1000);
create_unimplemented_device("i2c0", 0x4001d000, 0x1000);
create_unimplemented_device("i2c1", 0x4001e000, 0x1000);
create_unimplemented_device("i2c2", 0x4001f000, 0x1000);
create_unimplemented_device("standardDMA", 0x40028000, 0x1000);
create_unimplemented_device("flashController0", 0x40029000, 0x400);
create_unimplemented_device("icc0", 0x4002a000, 0x800);
create_unimplemented_device("icc1", 0x4002a800, 0x800);
create_unimplemented_device("adc", 0x40034000, 0x1000);
create_unimplemented_device("pulseTrainEngine", 0x4003c000, 0xa0);
create_unimplemented_device("oneWireMaster", 0x4003d000, 0x1000);
create_unimplemented_device("semaphore", 0x4003e000, 0x1000);
create_unimplemented_device("uart0", 0x40042000, 0x1000);
create_unimplemented_device("uart1", 0x40043000, 0x1000);
create_unimplemented_device("uart2", 0x40044000, 0x1000);
create_unimplemented_device("spi1", 0x40046000, 0x2000);
create_unimplemented_device("trng", 0x4004d000, 0x1000);
create_unimplemented_device("i2s", 0x40060000, 0x1000);
create_unimplemented_device("lowPowerControl", 0x40080000, 0x400);
create_unimplemented_device("gpio2", 0x40080400, 0x200);
create_unimplemented_device("lowPowerWatchdogTimer", 0x40080800, 0x400);
create_unimplemented_device("lowPowerTimer4", 0x40080c00, 0x400);
create_unimplemented_device("lowPowerTimer5", 0x40081000, 0x400);
create_unimplemented_device("lowPowerUART0", 0x40081400, 0x400);
create_unimplemented_device("lowPowerComparator", 0x40088000, 0x400);
create_unimplemented_device("spi0", 0x400be000, 0x400);
/*
* The MAX78000 user guide's base address map lists the CNN TX FIFO as
* beginning at 0x400c0400 and ending at 0x400c0400. Given that CNN_FIFO
* is listed as having data accessible up to offset 0x1000, the user
* guide is likely incorrect.
*/
create_unimplemented_device("cnnTxFIFO", 0x400c0400, 0x2000);
create_unimplemented_device("cnnGlobalControl", 0x50000000, 0x10000);
create_unimplemented_device("cnnx16quad0", 0x50100000, 0x40000);
create_unimplemented_device("cnnx16quad1", 0x50500000, 0x40000);
create_unimplemented_device("cnnx16quad2", 0x50900000, 0x40000);
create_unimplemented_device("cnnx16quad3", 0x50d00000, 0x40000);
}
static void max78000_soc_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = max78000_soc_realize;
}
static const TypeInfo max78000_soc_info = {
.name = TYPE_MAX78000_SOC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(MAX78000State),
.instance_init = max78000_soc_initfn,
.class_init = max78000_soc_class_init,
};
static void max78000_soc_types(void)
{
type_register_static(&max78000_soc_info);
}
type_init(max78000_soc_types)

50
hw/arm/max78000fthr.c Normal file
View file

@ -0,0 +1,50 @@
/*
* MAX78000FTHR Evaluation Board
*
* Copyright (c) 2025 Jackson Donaldson <jcksn@duck.com>
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "hw/boards.h"
#include "hw/qdev-properties.h"
#include "hw/qdev-clock.h"
#include "qemu/error-report.h"
#include "hw/arm/max78000_soc.h"
#include "hw/arm/boot.h"
/* 60MHz is the default, but other clocks can be selected. */
#define SYSCLK_FRQ 60000000ULL
static void max78000_init(MachineState *machine)
{
DeviceState *dev;
Clock *sysclk;
sysclk = clock_new(OBJECT(machine), "SYSCLK");
clock_set_hz(sysclk, SYSCLK_FRQ);
dev = qdev_new(TYPE_MAX78000_SOC);
object_property_add_child(OBJECT(machine), "soc", OBJECT(dev));
qdev_connect_clock_in(dev, "sysclk", sysclk);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
armv7m_load_kernel(ARM_CPU(first_cpu),
machine->kernel_filename,
0x00000000, FLASH_SIZE);
}
static void max78000_machine_init(MachineClass *mc)
{
static const char * const valid_cpu_types[] = {
ARM_CPU_TYPE_NAME("cortex-m4"),
NULL
};
mc->desc = "MAX78000FTHR Board (Cortex-M4 / (Unimplemented) RISC-V)";
mc->init = max78000_init;
mc->valid_cpu_types = valid_cpu_types;
}
DEFINE_MACHINE("max78000fthr", max78000_machine_init)

2
hw/arm/meson.build
View file

@ -27,6 +27,7 @@ arm_common_ss.add(when: 'CONFIG_OMAP', if_true: files('omap1.c'))
arm_common_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10.c', 'cubieboard.c')) arm_common_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10.c', 'cubieboard.c'))
arm_common_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', 'orangepi.c')) arm_common_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', 'orangepi.c'))
arm_common_ss.add(when: 'CONFIG_ALLWINNER_R40', if_true: files('allwinner-r40.c', 'bananapi_m2u.c')) arm_common_ss.add(when: 'CONFIG_ALLWINNER_R40', if_true: files('allwinner-r40.c', 'bananapi_m2u.c'))
arm_common_ss.add(when: 'CONFIG_MAX78000_SOC', if_true: files('max78000_soc.c'))
arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2836.c', 'raspi.c')) arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2836.c', 'raspi.c'))
arm_common_ss.add(when: ['CONFIG_RASPI', 'TARGET_AARCH64'], if_true: files('bcm2838.c', 'raspi4b.c')) arm_common_ss.add(when: ['CONFIG_RASPI', 'TARGET_AARCH64'], if_true: files('bcm2838.c', 'raspi4b.c'))
arm_common_ss.add(when: 'CONFIG_STM32F100_SOC', if_true: files('stm32f100_soc.c')) arm_common_ss.add(when: 'CONFIG_STM32F100_SOC', if_true: files('stm32f100_soc.c'))
@ -71,6 +72,7 @@ arm_ss.add(when: 'CONFIG_XEN', if_true: files(
arm_common_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmu-common.c')) arm_common_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmu-common.c'))
arm_common_ss.add(when: 'CONFIG_COLLIE', if_true: files('collie.c')) arm_common_ss.add(when: 'CONFIG_COLLIE', if_true: files('collie.c'))
arm_common_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4_boards.c')) arm_common_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4_boards.c'))
arm_common_ss.add(when: 'CONFIG_MAX78000FTHR', if_true: files('max78000fthr.c'))
arm_common_ss.add(when: 'CONFIG_NETDUINO2', if_true: files('netduino2.c')) arm_common_ss.add(when: 'CONFIG_NETDUINO2', if_true: files('netduino2.c'))
arm_common_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_peripherals.c')) arm_common_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_peripherals.c'))
arm_common_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2838_peripherals.c')) arm_common_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2838_peripherals.c'))

35
include/hw/arm/max78000_soc.h Normal file
View file

@ -0,0 +1,35 @@
/*
* MAX78000 SOC
*
* Copyright (c) 2025 Jackson Donaldson <jcksn@duck.com>
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#ifndef HW_ARM_MAX78000_SOC_H
#define HW_ARM_MAX78000_SOC_H
#include "hw/or-irq.h"
#include "hw/arm/armv7m.h"
#include "qom/object.h"
#define TYPE_MAX78000_SOC "max78000-soc"
OBJECT_DECLARE_SIMPLE_TYPE(MAX78000State, MAX78000_SOC)
#define FLASH_BASE_ADDRESS 0x10000000
#define FLASH_SIZE (512 * 1024)
#define SRAM_BASE_ADDRESS 0x20000000
#define SRAM_SIZE (128 * 1024)
struct MAX78000State {
SysBusDevice parent_obj;
ARMv7MState armv7m;
MemoryRegion sram;
MemoryRegion flash;
Clock *sysclk;
};
#endif