igvm: add support for initial register state load in native mode
Add IgvmNativeVpContextX64 struct holding the register state (see igvm spec), and the qigvm_x86_load_context() function to load the register state. Wire up using two new functions: qigvm_x86_set_vp_context() is called from igvm file handling code and stores the boot processor context. qigvm_x86_bsp_reset() is called from i386 target cpu reset code and loads the context into the cpu registers. Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> Reviewed-by: Luigi Leonardi <leonardi@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-ID: <20251029105555.2492276-5-kraxel@redhat.com>
This commit is contained in:
Gerd Hoffmann
parent
13abf2fcb7
commit
593fe98d74
6 changed files with 165 additions and 15 deletions
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@ -432,18 +432,6 @@ static int qigvm_directive_vp_context(QIgvm *ctx, const uint8_t *header_data,
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return 0;
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}
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/*
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* A confidential guest support object must be provided for setting
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* a VP context.
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*/
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if (!ctx->cgs) {
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error_setg(
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errp,
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"A VP context is present in the IGVM file but is not supported "
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"by the current system.");
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return -1;
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}
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data_handle = igvm_get_header_data(ctx->file, IGVM_HEADER_SECTION_DIRECTIVE,
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ctx->current_header_index);
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if (data_handle < 0) {
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@ -453,9 +441,21 @@ static int qigvm_directive_vp_context(QIgvm *ctx, const uint8_t *header_data,
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}
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data = (uint8_t *)igvm_get_buffer(ctx->file, data_handle);
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if (ctx->cgs) {
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result = ctx->cgsc->set_guest_state(
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vp_context->gpa, data, igvm_get_buffer_size(ctx->file, data_handle),
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CGS_PAGE_TYPE_VMSA, vp_context->vp_index, errp);
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} else if (target_arch() == SYS_EMU_TARGET_X86_64) {
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result = qigvm_x86_set_vp_context(data, vp_context->vp_index, errp);
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} else {
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error_setg(
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errp,
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"A VP context is present in the IGVM file but is not supported "
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"by the current system.");
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result = -1;
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}
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igvm_free_buffer(ctx->file, data_handle);
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if (result < 0) {
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return result;
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@ -23,5 +23,7 @@ int qigvm_process_file(IgvmCfg *igvm, ConfidentialGuestSupport *cgs,
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int qigvm_x86_get_mem_map_entry(int index,
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ConfidentialGuestMemoryMapEntry *entry,
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Error **errp);
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int qigvm_x86_set_vp_context(void *data, int index,
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Error **errp);
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#endif
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@ -19,3 +19,8 @@ int qigvm_x86_get_mem_map_entry(int index,
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{
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return -1;
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}
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int qigvm_x86_set_vp_context(void *data, int index, Error **errp)
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{
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return -1;
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}
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@ -8770,6 +8770,12 @@ static void x86_cpu_reset_hold(Object *obj, ResetType type)
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cs->halted = !cpu_is_bsp(cpu);
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#if defined(CONFIG_IGVM)
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if (cpu_is_bsp(cpu)) {
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qigvm_x86_bsp_reset(env);
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}
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#endif
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if (kvm_enabled()) {
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kvm_arch_reset_vcpu(cpu);
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}
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@ -2868,6 +2868,9 @@ void x86_cpu_dump_local_apic_state(CPUState *cs, int flags);
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#endif
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/* igvm.c */
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void qigvm_x86_bsp_reset(CPUX86State *env);
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/* cpu.c */
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bool cpu_is_bsp(X86CPU *cpu);
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@ -11,9 +11,115 @@
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "hw/i386/e820_memory_layout.h"
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#include "system/igvm.h"
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struct IgvmNativeVpContextX64 {
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uint64_t rax;
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uint64_t rcx;
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uint64_t rdx;
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uint64_t rbx;
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uint64_t rsp;
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uint64_t rbp;
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uint64_t rsi;
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uint64_t rdi;
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uint64_t r8;
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uint64_t r9;
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uint64_t r10;
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uint64_t r11;
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uint64_t r12;
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uint64_t r13;
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uint64_t r14;
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uint64_t r15;
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uint64_t rip;
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uint64_t rflags;
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uint64_t idtr_base;
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uint16_t idtr_limit;
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uint16_t reserved[2];
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uint16_t gdtr_limit;
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uint64_t gdtr_base;
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uint16_t code_selector;
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uint16_t code_attributes;
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uint32_t code_base;
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uint32_t code_limit;
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uint16_t data_selector;
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uint16_t data_attributes;
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uint32_t data_base;
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uint32_t data_limit;
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uint64_t gs_base;
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uint64_t cr0;
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uint64_t cr3;
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uint64_t cr4;
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uint64_t efer;
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};
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#define FLAGS_TO_SEGCACHE(flags) \
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(((unsigned int)flags) << 8)
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static void qigvm_x86_load_context(struct IgvmNativeVpContextX64 *context,
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CPUX86State *env)
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{
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cpu_load_efer(env, context->efer);
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cpu_x86_update_cr4(env, context->cr4);
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cpu_x86_update_cr0(env, context->cr0);
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cpu_x86_update_cr3(env, context->cr3);
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cpu_x86_load_seg_cache(
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env, R_CS, context->code_selector,
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context->code_base, context->code_limit,
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FLAGS_TO_SEGCACHE(context->code_attributes));
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cpu_x86_load_seg_cache(
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env, R_DS, context->data_selector,
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context->data_base, context->data_limit,
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FLAGS_TO_SEGCACHE(context->data_attributes));
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cpu_x86_load_seg_cache(
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env, R_ES, context->data_selector,
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context->data_base, context->data_limit,
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FLAGS_TO_SEGCACHE(context->data_attributes));
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cpu_x86_load_seg_cache(
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env, R_FS, context->data_selector,
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context->data_base, context->data_limit,
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FLAGS_TO_SEGCACHE(context->data_attributes));
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cpu_x86_load_seg_cache(
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env, R_GS, context->data_selector,
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context->data_base, context->data_limit,
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FLAGS_TO_SEGCACHE(context->data_attributes));
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cpu_x86_load_seg_cache(
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env, R_SS, context->data_selector,
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context->data_base, context->data_limit,
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FLAGS_TO_SEGCACHE(context->data_attributes));
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env->gdt.base = context->gdtr_base;
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env->gdt.limit = context->gdtr_limit;
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env->idt.base = context->idtr_base;
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env->idt.limit = context->idtr_limit;
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env->regs[R_EAX] = context->rax;
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env->regs[R_ECX] = context->rcx;
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env->regs[R_EDX] = context->rdx;
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env->regs[R_EBX] = context->rbx;
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env->regs[R_ESP] = context->rsp;
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env->regs[R_EBP] = context->rbp;
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env->regs[R_ESI] = context->rsi;
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env->regs[R_EDI] = context->rdi;
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#ifdef TARGET_X86_64
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env->regs[R_R8] = context->r8;
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env->regs[R_R9] = context->r9;
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env->regs[R_R10] = context->r10;
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env->regs[R_R11] = context->r11;
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env->regs[R_R12] = context->r12;
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env->regs[R_R13] = context->r13;
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env->regs[R_R14] = context->r14;
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env->regs[R_R15] = context->r15;
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#endif
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env->eip = context->rip;
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env->eflags = context->rflags;
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}
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/*
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* convert e820 table into igvm memory map
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*/
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@ -44,3 +150,31 @@ int qigvm_x86_get_mem_map_entry(int index,
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}
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return 0;
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}
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/*
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* set initial cpu context
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*/
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static struct IgvmNativeVpContextX64 *bsp_context;
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int qigvm_x86_set_vp_context(void *data, int index, Error **errp)
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{
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if (index != 0) {
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error_setg(errp, "context can be set for BSP only");
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return -1;
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}
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if (bsp_context == NULL) {
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bsp_context = g_new0(struct IgvmNativeVpContextX64, 1);
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}
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memcpy(bsp_context, data, sizeof(struct IgvmNativeVpContextX64));
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return 0;
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}
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void qigvm_x86_bsp_reset(CPUX86State *env)
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{
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if (bsp_context == NULL) {
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return;
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}
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qigvm_x86_load_context(bsp_context, env);
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}
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