From cacd8fb08d3f992ef9cdf4c26a2d28ced409cfd4 Mon Sep 17 00:00:00 2001 From: Nabih Estefan Date: Tue, 4 Nov 2025 23:37:42 +0000 Subject: [PATCH 1/3] hw/arm/ast27x0: Fix typo in LTPI address MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The address for LTPI has one more 0 that it should, bug introduced in commit 91064bea6b2d747a981cb3bd2904e56f443e6c67. Signed-off-by: Nabih Estefan Fixes: 91064bea6b2d ("aspeed: ast27x0: Map unimplemented devices in SoC memory") Reviewed-by: Cédric Le Goater Link: https://lore.kernel.org/qemu-devel/20251104233742.2147367-1-nabihestefan@google.com Signed-off-by: Cédric Le Goater --- hw/arm/aspeed_ast27x0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index c484bcd4e2..1e6f469538 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -87,11 +87,11 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = { [ASPEED_DEV_UART11] = 0x14C33A00, [ASPEED_DEV_UART12] = 0x14C33B00, [ASPEED_DEV_WDT] = 0x14C37000, + [ASPEED_DEV_LTPI] = 0x30000000, [ASPEED_DEV_PCIE_MMIO0] = 0x60000000, [ASPEED_DEV_PCIE_MMIO1] = 0x80000000, [ASPEED_DEV_PCIE_MMIO2] = 0xA0000000, [ASPEED_DEV_SPI_BOOT] = 0x100000000, - [ASPEED_DEV_LTPI] = 0x300000000, [ASPEED_DEV_SDRAM] = 0x400000000, }; From 510d5c61ad3eb1690b61c804d38c984527a5ea62 Mon Sep 17 00:00:00 2001 From: Jamin Lin Date: Thu, 6 Nov 2025 16:49:10 +0800 Subject: [PATCH 2/3] hw/arm/aspeed: Fix missing SPI IRQ connection causing DMA interrupt failure MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It did not connect SPI IRQ to the Interrupt Controller, so even the SPI model raised the IRQ, the interrupt was not received. The CPU therefore did not trigger an interrupt via the controller, and the firmware never received the interrupt. Fixes: 356b230ed13889e09d087a96498887de695df17e ("aspeed/soc: Add AST1030 support") Fixes: f25c0ae1079dc0b9de02676eb3e3949a09df9f41 ("aspeed/soc: Add AST2600 support") Fixes: 5dd883ab0635c9f715c77cc32622e458a0724581 ("aspeed/soc: Add AST2700 support") Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater Link: https://lore.kernel.org/qemu-devel/20251106084925.1253704-2-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater --- hw/arm/aspeed_ast10x0.c | 2 ++ hw/arm/aspeed_ast2600.c | 2 ++ hw/arm/aspeed_ast27x0.c | 2 ++ 3 files changed, 6 insertions(+) diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index 7f49c13391..ca487774ae 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -372,6 +372,8 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp) sc->memmap[ASPEED_DEV_SPI1 + i]); aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->spi[i]), 1, ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, + aspeed_soc_ast1030_get_irq(s, ASPEED_DEV_SPI1 + i)); } /* Secure Boot Controller */ diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index 498d1ecc07..4c5a42ea17 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -557,6 +557,8 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) sc->memmap[ASPEED_DEV_SPI1 + i]); aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->spi[i]), 1, ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, + aspeed_soc_ast2600_get_irq(s, ASPEED_DEV_SPI1 + i)); } /* EHCI */ diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 1e6f469538..95f155fcf1 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -831,6 +831,8 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp) sc->memmap[ASPEED_DEV_SPI0 + i]); aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->spi[i]), 1, ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, + aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_SPI0 + i)); } /* EHCI */ From e9a8b04dbb98fba7942b23b3ac5c35f2f0b9c4a0 Mon Sep 17 00:00:00 2001 From: Jamin Lin Date: Fri, 21 Nov 2025 13:01:08 +0800 Subject: [PATCH 3/3] hw/pci-host/aspeed_pcie: Update ASPEED PCIe Root Port capabilities and enable MSI to support hotplug MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch updates the ASPEED PCIe Root Port capability layout and interrupt handling to match the hardware-defined capability structure as documented in the PCI Express Controller (PCIE) chapter of the ASPEED SoC datasheet. The following capability offsets and fields are now aligned with the actual hardware implementation (validated using EVB config-space dumps via 'lspci -s -vvv'): - Added MSI capability at offset 0x50 and enabled 1-vector MSI support - Added PCI Express Capability structure at offset 0x80 - Added Secondary Subsystem Vendor ID (SSVID) at offset 0xC0 - Added AER capability at offset 0x100 - Implemented aer_vector() callback and MSI init/uninit hooks - Updated Root Port SSID to 0x1150 to reflect the platform default Enabling MSI is required for proper PCIe Hotplug event signaling. This change improves correctness and ensures QEMU Root Port behavior matches the behavior of ASPEED hardware and downstream kernel expectations. Signed-off-by: Jamin Lin Fixes: 2af56518fa91 ("hw/pci-host/aspeed: Add AST2600 PCIe Root Port and make address configurable") Reviewed-by: Cédric Le Goater Reviewed-by: Nabih Estefan Tested-by: Nabih Estefan Reviewed-by: Philippe Mathieu-Daudé Link: https://lore.kernel.org/qemu-devel/20251121050108.3407445-2-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater --- hw/pci-host/aspeed_pcie.c | 40 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 39 insertions(+), 1 deletion(-) diff --git a/hw/pci-host/aspeed_pcie.c b/hw/pci-host/aspeed_pcie.c index f7593444fc..1fc2c61772 100644 --- a/hw/pci-host/aspeed_pcie.c +++ b/hw/pci-host/aspeed_pcie.c @@ -68,6 +68,38 @@ static const TypeInfo aspeed_pcie_root_device_info = { * PCIe Root Port */ +#define ASPEED_PCIE_ROOT_PORT_MSI_OFFSET 0x50 +#define ASPEED_PCIE_ROOT_PORT_MSI_NR_VECTOR 1 +#define ASPEED_PCIE_ROOT_PORT_SSVID_OFFSET 0xC0 +#define ASPEED_PCIE_ROOT_PORT_EXP_OFFSET 0x80 +#define ASPEED_PCIE_ROOT_PORT_AER_OFFSET 0x100 + +static uint8_t aspeed_pcie_root_port_aer_vector(const PCIDevice *d) +{ + return 0; +} + +static int aspeed_pcie_root_port_interrupts_init(PCIDevice *d, Error **errp) +{ + int rc; + + rc = msi_init(d, ASPEED_PCIE_ROOT_PORT_MSI_OFFSET, + ASPEED_PCIE_ROOT_PORT_MSI_NR_VECTOR, + PCI_MSI_FLAGS_MASKBIT & PCI_MSI_FLAGS_64BIT, + PCI_MSI_FLAGS_MASKBIT & PCI_MSI_FLAGS_MASKBIT, + errp); + if (rc < 0) { + assert(rc == -ENOTSUP); + } + + return rc; +} + +static void aspeed_pcie_root_port_interrupts_uninit(PCIDevice *d) +{ + msi_uninit(d); +} + static void aspeed_pcie_root_port_class_init(ObjectClass *klass, const void *data) { @@ -80,7 +112,13 @@ static void aspeed_pcie_root_port_class_init(ObjectClass *klass, k->device_id = 0x1150; dc->user_creatable = true; - rpc->aer_offset = 0x100; + rpc->aer_vector = aspeed_pcie_root_port_aer_vector; + rpc->interrupts_init = aspeed_pcie_root_port_interrupts_init; + rpc->interrupts_uninit = aspeed_pcie_root_port_interrupts_uninit; + rpc->exp_offset = ASPEED_PCIE_ROOT_PORT_EXP_OFFSET; + rpc->aer_offset = ASPEED_PCIE_ROOT_PORT_AER_OFFSET; + rpc->ssvid_offset = ASPEED_PCIE_ROOT_PORT_SSVID_OFFSET; + rpc->ssid = 0x1150; } static const TypeInfo aspeed_pcie_root_port_info = {