target/riscv: Move cpu_get_tb_cpu_state to tcg-cpu.c
This function is only relevant to tcg. Move it to a tcg-specific file. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
9da84372c4
commit
5b1c93be57
2 changed files with 98 additions and 97 deletions
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@ -135,103 +135,6 @@ bool riscv_env_smode_dbltrp_enabled(CPURISCVState *env, bool virt)
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#endif
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}
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void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
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uint64_t *cs_base, uint32_t *pflags)
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{
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RISCVCPU *cpu = env_archcpu(env);
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RISCVExtStatus fs, vs;
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uint32_t flags = 0;
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bool pm_signext = riscv_cpu_virt_mem_enabled(env);
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*pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
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*cs_base = 0;
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if (cpu->cfg.ext_zve32x) {
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/*
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* If env->vl equals to VLMAX, we can use generic vector operation
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* expanders (GVEC) to accerlate the vector operations.
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* However, as LMUL could be a fractional number. The maximum
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* vector size can be operated might be less than 8 bytes,
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* which is not supported by GVEC. So we set vl_eq_vlmax flag to true
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* only when maxsz >= 8 bytes.
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*/
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/* lmul encoded as in DisasContext::lmul */
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int8_t lmul = sextract32(FIELD_EX64(env->vtype, VTYPE, VLMUL), 0, 3);
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uint32_t vsew = FIELD_EX64(env->vtype, VTYPE, VSEW);
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uint32_t vlmax = vext_get_vlmax(cpu->cfg.vlenb, vsew, lmul);
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uint32_t maxsz = vlmax << vsew;
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bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) &&
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(maxsz >= 8);
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flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill);
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flags = FIELD_DP32(flags, TB_FLAGS, SEW, vsew);
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flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
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FIELD_EX64(env->vtype, VTYPE, VLMUL));
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flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax);
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flags = FIELD_DP32(flags, TB_FLAGS, VTA,
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FIELD_EX64(env->vtype, VTYPE, VTA));
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flags = FIELD_DP32(flags, TB_FLAGS, VMA,
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FIELD_EX64(env->vtype, VTYPE, VMA));
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flags = FIELD_DP32(flags, TB_FLAGS, VSTART_EQ_ZERO, env->vstart == 0);
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} else {
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flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);
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}
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if (cpu_get_fcfien(env)) {
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/*
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* For Forward CFI, only the expectation of a lpad at
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* the start of the block is tracked via env->elp. env->elp
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* is turned on during jalr translation.
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*/
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flags = FIELD_DP32(flags, TB_FLAGS, FCFI_LP_EXPECTED, env->elp);
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flags = FIELD_DP32(flags, TB_FLAGS, FCFI_ENABLED, 1);
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}
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if (cpu_get_bcfien(env)) {
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flags = FIELD_DP32(flags, TB_FLAGS, BCFI_ENABLED, 1);
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}
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#ifdef CONFIG_USER_ONLY
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fs = EXT_STATUS_DIRTY;
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vs = EXT_STATUS_DIRTY;
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#else
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flags = FIELD_DP32(flags, TB_FLAGS, PRIV, env->priv);
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flags |= riscv_env_mmu_index(env, 0);
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fs = get_field(env->mstatus, MSTATUS_FS);
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vs = get_field(env->mstatus, MSTATUS_VS);
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if (env->virt_enabled) {
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flags = FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, 1);
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/*
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* Merge DISABLED and !DIRTY states using MIN.
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* We will set both fields when dirtying.
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*/
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fs = MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS));
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vs = MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS));
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}
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/* With Zfinx, floating point is enabled/disabled by Smstateen. */
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if (!riscv_has_ext(env, RVF)) {
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fs = (smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR) == RISCV_EXCP_NONE)
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? EXT_STATUS_DIRTY : EXT_STATUS_DISABLED;
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}
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if (cpu->cfg.debug && !icount_enabled()) {
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flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled);
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}
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#endif
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flags = FIELD_DP32(flags, TB_FLAGS, FS, fs);
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flags = FIELD_DP32(flags, TB_FLAGS, VS, vs);
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flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl);
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flags = FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env));
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flags = FIELD_DP32(flags, TB_FLAGS, PM_PMM, riscv_pm_get_pmm(env));
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flags = FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext);
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*pflags = flags;
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}
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RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env)
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{
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#ifndef CONFIG_USER_ONLY
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@ -36,6 +36,7 @@
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#ifndef CONFIG_USER_ONLY
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#include "hw/boards.h"
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#include "system/tcg.h"
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#include "exec/icount.h"
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#endif
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/* Hash that stores user set extensions */
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@ -97,6 +98,103 @@ static int riscv_cpu_mmu_index(CPUState *cs, bool ifetch)
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return riscv_env_mmu_index(cpu_env(cs), ifetch);
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}
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void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
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uint64_t *cs_base, uint32_t *pflags)
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{
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RISCVCPU *cpu = env_archcpu(env);
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RISCVExtStatus fs, vs;
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uint32_t flags = 0;
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bool pm_signext = riscv_cpu_virt_mem_enabled(env);
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*pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
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*cs_base = 0;
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if (cpu->cfg.ext_zve32x) {
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/*
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* If env->vl equals to VLMAX, we can use generic vector operation
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* expanders (GVEC) to accerlate the vector operations.
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* However, as LMUL could be a fractional number. The maximum
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* vector size can be operated might be less than 8 bytes,
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* which is not supported by GVEC. So we set vl_eq_vlmax flag to true
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* only when maxsz >= 8 bytes.
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*/
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/* lmul encoded as in DisasContext::lmul */
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int8_t lmul = sextract32(FIELD_EX64(env->vtype, VTYPE, VLMUL), 0, 3);
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uint32_t vsew = FIELD_EX64(env->vtype, VTYPE, VSEW);
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uint32_t vlmax = vext_get_vlmax(cpu->cfg.vlenb, vsew, lmul);
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uint32_t maxsz = vlmax << vsew;
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bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) &&
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(maxsz >= 8);
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flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill);
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flags = FIELD_DP32(flags, TB_FLAGS, SEW, vsew);
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flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
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FIELD_EX64(env->vtype, VTYPE, VLMUL));
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flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax);
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flags = FIELD_DP32(flags, TB_FLAGS, VTA,
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FIELD_EX64(env->vtype, VTYPE, VTA));
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flags = FIELD_DP32(flags, TB_FLAGS, VMA,
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FIELD_EX64(env->vtype, VTYPE, VMA));
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flags = FIELD_DP32(flags, TB_FLAGS, VSTART_EQ_ZERO, env->vstart == 0);
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} else {
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flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);
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}
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if (cpu_get_fcfien(env)) {
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/*
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* For Forward CFI, only the expectation of a lpad at
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* the start of the block is tracked via env->elp. env->elp
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* is turned on during jalr translation.
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*/
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flags = FIELD_DP32(flags, TB_FLAGS, FCFI_LP_EXPECTED, env->elp);
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flags = FIELD_DP32(flags, TB_FLAGS, FCFI_ENABLED, 1);
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}
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if (cpu_get_bcfien(env)) {
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flags = FIELD_DP32(flags, TB_FLAGS, BCFI_ENABLED, 1);
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}
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#ifdef CONFIG_USER_ONLY
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fs = EXT_STATUS_DIRTY;
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vs = EXT_STATUS_DIRTY;
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#else
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flags = FIELD_DP32(flags, TB_FLAGS, PRIV, env->priv);
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flags |= riscv_env_mmu_index(env, 0);
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fs = get_field(env->mstatus, MSTATUS_FS);
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vs = get_field(env->mstatus, MSTATUS_VS);
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if (env->virt_enabled) {
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flags = FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, 1);
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/*
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* Merge DISABLED and !DIRTY states using MIN.
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* We will set both fields when dirtying.
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*/
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fs = MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS));
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vs = MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS));
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}
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/* With Zfinx, floating point is enabled/disabled by Smstateen. */
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if (!riscv_has_ext(env, RVF)) {
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fs = (smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR) == RISCV_EXCP_NONE)
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? EXT_STATUS_DIRTY : EXT_STATUS_DISABLED;
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}
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if (cpu->cfg.debug && !icount_enabled()) {
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flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled);
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}
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#endif
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flags = FIELD_DP32(flags, TB_FLAGS, FS, fs);
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flags = FIELD_DP32(flags, TB_FLAGS, VS, vs);
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flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl);
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flags = FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env));
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flags = FIELD_DP32(flags, TB_FLAGS, PM_PMM, riscv_pm_get_pmm(env));
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flags = FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext);
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*pflags = flags;
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}
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static void riscv_cpu_synchronize_from_tb(CPUState *cs,
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const TranslationBlock *tb)
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{
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