target/loongarch: Add CSR_PWCH write helper function

Bit HPTW_EN in register CSR_PWCH controls enabling hardware page
table walker feature when PTW feature is enabled. Otherwise it is
reserved bit.

Here add register CSR_PWCH write helper function.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
This commit is contained in:
Bibo Mao 2025-07-16 11:23:13 +08:00
parent 6447334a31
commit 5cba5a518b
4 changed files with 19 additions and 0 deletions

View file

@ -105,6 +105,8 @@ FIELD(CSR_PWCH, DIR3_BASE, 0, 6)
FIELD(CSR_PWCH, DIR3_WIDTH, 6, 6)
FIELD(CSR_PWCH, DIR4_BASE, 12, 6)
FIELD(CSR_PWCH, DIR4_WIDTH, 18, 6)
FIELD(CSR_PWCH, HPTW_EN, 24, 1)
FIELD(CSR_PWCH, RESERVE, 25, 7)
#define LOONGARCH_CSR_STLBPS 0x1e /* Stlb page size */
FIELD(CSR_STLBPS, PS, 0, 5)

View file

@ -163,3 +163,18 @@ target_ulong helper_csrwr_pwcl(CPULoongArchState *env, target_ulong val)
env->CSR_PWCL = val;
return old_v;
}
target_ulong helper_csrwr_pwch(CPULoongArchState *env, target_ulong val)
{
uint8_t has_ptw;
int64_t old_v = env->CSR_PWCH;
val = FIELD_DP64(val, CSR_PWCH, RESERVE, 0);
has_ptw = FIELD_EX32(env->cpucfg[2], CPUCFG2, HPTW);
if (!has_ptw) {
val = FIELD_DP64(val, CSR_PWCH, HPTW_EN, 0);
}
env->CSR_PWCH = val;
return old_v;
}

View file

@ -107,6 +107,7 @@ DEF_HELPER_2(csrwr_asid, i64, env, tl)
DEF_HELPER_2(csrwr_tcfg, i64, env, tl)
DEF_HELPER_2(csrwr_ticlr, i64, env, tl)
DEF_HELPER_2(csrwr_pwcl, i64, env, tl)
DEF_HELPER_2(csrwr_pwch, i64, env, tl)
DEF_HELPER_2(iocsrrd_b, i64, env, tl)
DEF_HELPER_2(iocsrrd_h, i64, env, tl)
DEF_HELPER_2(iocsrrd_w, i64, env, tl)

View file

@ -79,6 +79,7 @@ void loongarch_csr_translate_init(void)
SET_CSR_FUNC(ASID, NULL, gen_helper_csrwr_asid);
SET_CSR_FUNC(PGD, gen_helper_csrrd_pgd, NULL);
SET_CSR_FUNC(PWCL, NULL, gen_helper_csrwr_pwcl);
SET_CSR_FUNC(PWCH, NULL, gen_helper_csrwr_pwch);
SET_CSR_FUNC(CPUID, gen_helper_csrrd_cpuid, NULL);
SET_CSR_FUNC(TCFG, NULL, gen_helper_csrwr_tcfg);
SET_CSR_FUNC(TVAL, gen_helper_csrrd_tval, NULL);