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target/microblaze: Convert CPUMBState::res_addr field to uint32_t type

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CPUMBState::@res_addr field is used as u32 since commit
cfeea807e5 ("target-microblaze: Tighten up TCGv_i32 vs
TCGv type usage"). Convert it as such, bumping the migration
version. Use the RES_ADDR_NONE definition when appropriate.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20251015180115.97493-8-philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2025-10-08 06:58:51 +02:00
parent 2c12ba4d8b
commit 5dfe024f9e
3 changed files with 13 additions and 12 deletions
Download patch file Download diff file Expand all files Collapse all files

2
target/microblaze/cpu.h
View file

@ -259,7 +259,7 @@ struct CPUArchState {
/* lwx/swx reserved address */
#define RES_ADDR_NONE 0xffffffff /* Use 0xffffffff to indicate no reservation */
target_ulong res_addr;
uint32_t res_addr;
uint32_t res_val;
/* Internal flags. */

6
target/microblaze/machine.c
View file

@ -78,7 +78,7 @@ static const VMStateField vmstate_env_fields[] = {
VMSTATE_UINT32(iflags, CPUMBState),
VMSTATE_UINT32(res_val, CPUMBState),
VMSTATE_UINTTL(res_addr, CPUMBState),
VMSTATE_UINT32(res_addr, CPUMBState),
VMSTATE_STRUCT(mmu, CPUMBState, 0, vmstate_mmu, MicroBlazeMMU),
@ -87,8 +87,8 @@ static const VMStateField vmstate_env_fields[] = {
static const VMStateDescription vmstate_env = {
.name = "env",
.version_id = 0,
.minimum_version_id = 0,
.version_id = 1,
.minimum_version_id = 1,
.fields = vmstate_env_fields,
};

17
target/microblaze/translate.c
View file

@ -55,7 +55,7 @@ static TCGv_i32 cpu_imm;
static TCGv_i32 cpu_bvalue;
static TCGv_i32 cpu_btarget;
static TCGv_i32 cpu_iflags;
static TCGv cpu_res_addr;
static TCGv_i32 cpu_res_addr;
static TCGv_i32 cpu_res_val;
/* This is the state at translation time. */
@ -857,7 +857,7 @@ static bool trans_lwx(DisasContext *dc, arg_typea *arg)
tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index,
mo_endian(dc) | MO_UL);
tcg_gen_mov_tl(cpu_res_addr, addr);
tcg_gen_mov_i32(cpu_res_addr, addr);
if (arg->rd) {
tcg_gen_mov_i32(cpu_R[arg->rd], cpu_res_val);
@ -1024,7 +1024,7 @@ static bool trans_swx(DisasContext *dc, arg_typea *arg)
* branch, but we know we can use the equal version in the global.
* In either case, addr is no longer needed.
*/
tcg_gen_brcond_tl(TCG_COND_NE, cpu_res_addr, addr, swx_fail);
tcg_gen_brcond_i32(TCG_COND_NE, cpu_res_addr, addr, swx_fail);
/*
* Compare the value loaded during lwx with current contents of
@ -1052,7 +1052,7 @@ static bool trans_swx(DisasContext *dc, arg_typea *arg)
* Prevent the saved address from working again without another ldx.
* Akin to the pseudocode setting reservation = 0.
*/
tcg_gen_movi_tl(cpu_res_addr, -1);
tcg_gen_movi_i32(cpu_res_addr, RES_ADDR_NONE);
return true;
}
@ -1173,7 +1173,7 @@ static bool trans_brk(DisasContext *dc, arg_typea_br *arg)
tcg_gen_movi_i32(cpu_R[arg->rd], dc->base.pc_next);
}
tcg_gen_ori_i32(cpu_msr, cpu_msr, MSR_BIP);
tcg_gen_movi_tl(cpu_res_addr, -1);
tcg_gen_movi_i32(cpu_res_addr, RES_ADDR_NONE);
dc->base.is_jmp = DISAS_EXIT;
return true;
@ -1194,7 +1194,7 @@ static bool trans_brki(DisasContext *dc, arg_typeb_br *arg)
if (arg->rd) {
tcg_gen_movi_i32(cpu_R[arg->rd], dc->base.pc_next);
}
tcg_gen_movi_tl(cpu_res_addr, -1);
tcg_gen_movi_i32(cpu_res_addr, RES_ADDR_NONE);
#ifdef CONFIG_USER_ONLY
switch (imm) {
@ -1885,6 +1885,7 @@ void mb_tcg_init(void)
tcg_global_mem_new_i32(tcg_env, i32s[i].ofs, i32s[i].name);
}
cpu_res_addr =
tcg_global_mem_new(tcg_env, offsetof(CPUMBState, res_addr), "res_addr");
cpu_res_addr = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUMBState, res_addr),
"res_addr");
}