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target/{arm, riscv}/common-semi-target: eradicate target_ulong

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We replace mechanically with uint64_t.
There is no semantic change, and allows us to extract a proper API from
this set of functions.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-ID: <20250822150058.18692-7-pierrick.bouvier@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-ID: <20250922093711.2768983-10-alex.bennee@linaro.org>
This commit is contained in:
Pierrick Bouvier 2025-09-22 10:36:54 +01:00 • committed by Alex Bennée
parent 2131f0dcdf
commit 632308c591
2 changed files with 6 additions and 6 deletions
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6
target/arm/common-semi-target.h
View file

@ -12,7 +12,7 @@
#include "target/arm/cpu-qom.h"
static inline target_ulong common_semi_arg(CPUState *cs, int argno)
static inline uint64_t common_semi_arg(CPUState *cs, int argno)
{
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
@ -23,7 +23,7 @@ static inline target_ulong common_semi_arg(CPUState *cs, int argno)
}
}
static inline void common_semi_set_ret(CPUState *cs, target_ulong ret)
static inline void common_semi_set_ret(CPUState *cs, uint64_t ret)
{
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
@ -44,7 +44,7 @@ static inline bool is_64bit_semihosting(CPUArchState *env)
return is_a64(env);
}
static inline target_ulong common_semi_stack_bottom(CPUState *cs)
static inline uint64_t common_semi_stack_bottom(CPUState *cs)
{
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;

6
target/riscv/common-semi-target.h
View file

@ -11,14 +11,14 @@
#ifndef TARGET_RISCV_COMMON_SEMI_TARGET_H
#define TARGET_RISCV_COMMON_SEMI_TARGET_H
static inline target_ulong common_semi_arg(CPUState *cs, int argno)
static inline uint64_t common_semi_arg(CPUState *cs, int argno)
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
return env->gpr[xA0 + argno];
}
static inline void common_semi_set_ret(CPUState *cs, target_ulong ret)
static inline void common_semi_set_ret(CPUState *cs, uint64_t ret)
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
@ -35,7 +35,7 @@ static inline bool common_semi_sys_exit_is_extended(CPUState *cs)
return is_64bit_semihosting(cpu_env(cs));
}
static inline target_ulong common_semi_stack_bottom(CPUState *cs)
static inline uint64_t common_semi_stack_bottom(CPUState *cs)
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;