intel_iommu: Add PRI operations support
Implement the PRI callbacks in vtd_iommu_ops. Signed-off-by: Clement Mathieu--Drif <clement.mathieu--drif@eviden.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-ID: <20250901111630.1018573-6-clement.mathieu--drif@eviden.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
CLEMENT MATHIEU--DRIF
Michael S. Tsirkin
parent
b84e1e0730
commit
676757e50c
3 changed files with 277 additions and 0 deletions
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@ -45,6 +45,8 @@
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((ce)->val[1] & VTD_SM_CONTEXT_ENTRY_RID2PASID_MASK)
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#define VTD_CE_GET_PASID_DIR_TABLE(ce) \
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((ce)->val[0] & VTD_PASID_DIR_BASE_ADDR_MASK)
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#define VTD_CE_GET_PRE(ce) \
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((ce)->val[0] & VTD_SM_CONTEXT_ENTRY_PRE)
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/* pe operations */
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#define VTD_PE_GET_TYPE(pe) ((pe)->val[0] & VTD_SM_PASID_ENTRY_PGTT)
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@ -1838,6 +1840,7 @@ static const bool vtd_qualified_faults[] = {
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[VTD_FR_FS_NON_CANONICAL] = true,
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[VTD_FR_FS_PAGING_ENTRY_US] = true,
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[VTD_FR_SM_WRITE] = true,
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[VTD_FR_SM_PRE_ABS] = true,
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[VTD_FR_SM_INTERRUPT_ADDR] = true,
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[VTD_FR_FS_BIT_UPDATE_FAILED] = true,
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[VTD_FR_MAX] = false,
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@ -3152,6 +3155,59 @@ static bool vtd_process_device_piotlb_desc(IntelIOMMUState *s,
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return true;
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}
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static bool vtd_process_page_group_response_desc(IntelIOMMUState *s,
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VTDInvDesc *inv_desc)
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{
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VTDAddressSpace *vtd_dev_as;
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bool pasid_present;
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uint8_t response_code;
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uint16_t rid;
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uint32_t pasid;
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uint16_t prgi;
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IOMMUPRIResponse response;
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if ((inv_desc->lo & VTD_INV_DESC_PGRESP_RSVD_LO) ||
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(inv_desc->hi & VTD_INV_DESC_PGRESP_RSVD_HI)) {
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error_report_once("%s: invalid page group response desc: hi=%"PRIx64
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", lo=%"PRIx64" (reserved nonzero)", __func__,
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inv_desc->hi, inv_desc->lo);
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return false;
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}
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pasid_present = VTD_INV_DESC_PGRESP_PP(inv_desc->lo);
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response_code = VTD_INV_DESC_PGRESP_RC(inv_desc->lo);
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rid = VTD_INV_DESC_PGRESP_RID(inv_desc->lo);
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pasid = VTD_INV_DESC_PGRESP_PASID(inv_desc->lo);
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prgi = VTD_INV_DESC_PGRESP_PRGI(inv_desc->hi);
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if (!pasid_present) {
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error_report_once("Page group response without PASID is"
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"not supported yet");
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return false;
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}
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vtd_dev_as = vtd_get_as_by_sid_and_pasid(s, rid, pasid);
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if (!vtd_dev_as) {
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return true;
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}
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response.prgi = prgi;
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if (response_code == 0x0u) {
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response.response_code = IOMMU_PRI_RESP_SUCCESS;
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} else if (response_code == 0x1u) {
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response.response_code = IOMMU_PRI_RESP_INVALID_REQUEST;
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} else {
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response.response_code = IOMMU_PRI_RESP_FAILURE;
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}
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if (vtd_dev_as->pri_notifier) {
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vtd_dev_as->pri_notifier->notify(vtd_dev_as->pri_notifier, &response);
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}
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return true;
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}
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static bool vtd_process_device_iotlb_desc(IntelIOMMUState *s,
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VTDInvDesc *inv_desc)
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{
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@ -3252,6 +3308,13 @@ static bool vtd_process_inv_desc(IntelIOMMUState *s)
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}
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break;
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case VTD_INV_DESC_PGRESP:
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trace_vtd_inv_desc("page group response", inv_desc.hi, inv_desc.lo);
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if (!vtd_process_page_group_response_desc(s, &inv_desc)) {
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return false;
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}
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break;
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/*
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* TODO: the entity of below two cases will be implemented in future series.
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* To make guest (which integrates scalable mode support patch set in
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@ -4864,6 +4927,194 @@ static ssize_t vtd_ats_request_translation(PCIBus *bus, void *opaque,
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return res_index;
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}
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/* 11.4.11.3 : The number of entries in the page request queue is 2^(PQS + 7) */
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static inline uint64_t vtd_prq_size(IntelIOMMUState *s)
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{
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return 1ULL << ((vtd_get_quad(s, DMAR_PQA_REG) & VTD_PQA_SIZE) + 7);
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}
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/**
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* Return true if the bit is accessible and correctly set, false otherwise
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*/
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static bool vtd_check_pre_bit(VTDAddressSpace *vtd_as, hwaddr addr,
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uint16_t sid, bool is_write)
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{
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int ret;
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IntelIOMMUState *s = vtd_as->iommu_state;
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uint8_t bus_n = pci_bus_num(vtd_as->bus);
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VTDContextEntry ce;
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bool is_fpd_set = false;
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ret = vtd_dev_to_context_entry(s, bus_n, vtd_as->devfn, &ce);
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if (ret) {
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goto error_report;
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}
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if (!VTD_CE_GET_PRE(&ce)) {
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ret = -VTD_FR_SM_PRE_ABS;
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goto error_get_fpd_and_report;
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}
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return true;
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error_get_fpd_and_report:
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/* Try to get fpd (may not work but we are already on an error path) */
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is_fpd_set = ce.lo & VTD_CONTEXT_ENTRY_FPD;
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vtd_ce_get_pasid_fpd(s, &ce, &is_fpd_set, vtd_as->pasid);
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error_report:
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vtd_report_fault(s, -ret, is_fpd_set, sid, addr, is_write,
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vtd_as->pasid != PCI_NO_PASID, vtd_as->pasid);
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return false;
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}
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/* Logic described in section 7.5 */
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static void vtd_generate_page_request_event(IntelIOMMUState *s,
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uint32_t old_pr_status)
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{
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uint32_t current_pectl = vtd_get_long(s, DMAR_PECTL_REG);
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/*
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* Hardware evaluates PPR and PRO fields in the Page Request Status Register
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* and if any of them is set, Page Request Event is not generated
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*/
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if (old_pr_status & (VTD_PR_STATUS_PRO | VTD_PR_STATUS_PPR)) {
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return;
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}
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vtd_set_clear_mask_long(s, DMAR_PECTL_REG, 0, VTD_PR_PECTL_IP);
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if (!(current_pectl & VTD_PR_PECTL_IM)) {
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vtd_set_clear_mask_long(s, DMAR_PECTL_REG, VTD_PR_PECTL_IP, 0);
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vtd_generate_interrupt(s, DMAR_PEADDR_REG, DMAR_PEDATA_REG);
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}
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}
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/* When calling this function, we known that we are in scalable mode */
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static int vtd_pri_perform_implicit_invalidation(VTDAddressSpace *vtd_as,
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hwaddr addr)
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{
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IntelIOMMUState *s = vtd_as->iommu_state;
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VTDContextEntry ce;
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VTDPASIDEntry pe;
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uint16_t pgtt;
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uint16_t domain_id;
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int ret = vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus),
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vtd_as->devfn, &ce);
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if (ret) {
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return -EINVAL;
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}
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ret = vtd_ce_get_rid2pasid_entry(s, &ce, &pe, vtd_as->pasid);
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if (ret) {
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return -EINVAL;
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}
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pgtt = VTD_PE_GET_TYPE(&pe);
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domain_id = VTD_SM_PASID_ENTRY_DID(pe.val[1]);
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ret = 0;
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switch (pgtt) {
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case VTD_SM_PASID_ENTRY_FLT:
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vtd_piotlb_page_invalidate(s, domain_id, vtd_as->pasid, addr, 0);
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break;
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/* Room for other pgtt values */
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default:
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error_report_once("Translation type not supported yet : %d", pgtt);
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ret = -EINVAL;
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break;
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}
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return ret;
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}
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/* Page Request Descriptor : 7.4.1.1 */
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static int vtd_pri_request_page(PCIBus *bus, void *opaque, int devfn,
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uint32_t pasid, bool priv_req, bool exec_req,
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hwaddr addr, bool lpig, uint16_t prgi,
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bool is_read, bool is_write)
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{
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IntelIOMMUState *s = opaque;
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VTDAddressSpace *vtd_as;
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vtd_as = vtd_find_add_as(s, bus, devfn, pasid);
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uint64_t queue_addr_reg = vtd_get_quad(s, DMAR_PQA_REG);
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uint64_t queue_tail_offset_reg = vtd_get_quad(s, DMAR_PQT_REG);
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uint64_t new_queue_tail_offset = (
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(queue_tail_offset_reg + VTD_PQA_ENTRY_SIZE) %
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(vtd_prq_size(s) * VTD_PQA_ENTRY_SIZE));
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uint64_t queue_head_offset_reg = vtd_get_quad(s, DMAR_PQH_REG);
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hwaddr queue_tail = (queue_addr_reg & VTD_PQA_ADDR) + queue_tail_offset_reg;
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uint32_t old_pr_status = vtd_get_long(s, DMAR_PRS_REG);
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uint16_t sid = PCI_BUILD_BDF(pci_bus_num(vtd_as->bus), vtd_as->devfn);
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VTDPRDesc desc;
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if (!(s->ecap & VTD_ECAP_PRS)) {
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return -EPERM;
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}
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/*
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* No need to check if scalable mode is enabled as we already known that
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* VTD_ECAP_PRS is set (see vtd_decide_config)
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*/
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/* We do not support PRI without PASID */
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if (vtd_as->pasid == PCI_NO_PASID) {
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return -EPERM;
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}
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if (exec_req && !is_read) {
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return -EINVAL;
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}
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/* Check PRE bit in the scalable mode context entry */
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if (!vtd_check_pre_bit(vtd_as, addr, sid, is_write)) {
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return -EPERM;
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}
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if (old_pr_status & VTD_PR_STATUS_PRO) {
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/*
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* No action is taken by hardware to report a fault
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* or generate an event
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*/
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return -ENOSPC;
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}
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/* Check for overflow */
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if (new_queue_tail_offset == queue_head_offset_reg) {
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vtd_set_clear_mask_long(s, DMAR_PRS_REG, 0, VTD_PR_STATUS_PRO);
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vtd_generate_page_request_event(s, old_pr_status);
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return -ENOSPC;
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}
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if (vtd_pri_perform_implicit_invalidation(vtd_as, addr)) {
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return -EINVAL;
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}
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desc.lo = VTD_PRD_TYPE | VTD_PRD_PP(true) | VTD_PRD_RID(sid) |
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VTD_PRD_PASID(vtd_as->pasid) | VTD_PRD_PMR(priv_req);
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desc.hi = VTD_PRD_RDR(is_read) | VTD_PRD_WRR(is_write) |
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VTD_PRD_LPIG(lpig) | VTD_PRD_PRGI(prgi) | VTD_PRD_ADDR(addr);
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desc.lo = cpu_to_le64(desc.lo);
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desc.hi = cpu_to_le64(desc.hi);
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if (dma_memory_write(&address_space_memory, queue_tail, &desc, sizeof(desc),
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MEMTXATTRS_UNSPECIFIED)) {
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error_report_once("IO error, the PQ tail cannot be updated");
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return -EIO;
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}
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/* increment the tail register and set the pending request bit */
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vtd_set_quad(s, DMAR_PQT_REG, new_queue_tail_offset);
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/*
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* read status again so that the kernel does not miss a request.
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* in some cases, we can trigger an unecessary interrupt but this strategy
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* drastically improves performance as we don't need to take a lock.
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*/
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old_pr_status = vtd_get_long(s, DMAR_PRS_REG);
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if (!(old_pr_status & VTD_PR_STATUS_PPR)) {
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vtd_set_clear_mask_long(s, DMAR_PRS_REG, 0, VTD_PR_STATUS_PPR);
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vtd_generate_page_request_event(s, old_pr_status);
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}
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return 0;
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}
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static void vtd_init_iotlb_notifier(PCIBus *bus, void *opaque, int devfn,
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IOMMUNotifier *n, IOMMUNotify fn,
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void *user_opaque)
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@ -4905,6 +5156,26 @@ static void vtd_unregister_iotlb_notifier(PCIBus *bus, void *opaque,
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memory_region_unregister_iommu_notifier(MEMORY_REGION(&vtd_as->iommu), n);
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}
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static void vtd_pri_register_notifier(PCIBus *bus, void *opaque, int devfn,
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uint32_t pasid, IOMMUPRINotifier *notifier)
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{
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IntelIOMMUState *s = opaque;
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VTDAddressSpace *vtd_as;
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vtd_as = vtd_find_add_as(s, bus, devfn, pasid);
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vtd_as->pri_notifier = notifier;
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}
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static void vtd_pri_unregister_notifier(PCIBus *bus, void *opaque,
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int devfn, uint32_t pasid)
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{
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IntelIOMMUState *s = opaque;
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VTDAddressSpace *vtd_as;
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vtd_as = vtd_find_add_as(s, bus, devfn, pasid);
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vtd_as->pri_notifier = NULL;
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}
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static PCIIOMMUOps vtd_iommu_ops = {
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.get_address_space = vtd_host_dma_iommu,
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.set_iommu_device = vtd_dev_set_iommu_device,
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@ -4914,6 +5185,9 @@ static PCIIOMMUOps vtd_iommu_ops = {
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.register_iotlb_notifier = vtd_register_iotlb_notifier,
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.unregister_iotlb_notifier = vtd_unregister_iotlb_notifier,
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.ats_request_translation = vtd_ats_request_translation,
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.pri_register_notifier = vtd_pri_register_notifier,
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.pri_unregister_notifier = vtd_pri_unregister_notifier,
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.pri_request_page = vtd_pri_request_page,
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};
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static bool vtd_decide_config(IntelIOMMUState *s, Error **errp)
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@ -315,6 +315,8 @@ typedef enum VTDFaultReason {
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* request while disabled */
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VTD_FR_IR_SID_ERR = 0x26, /* Invalid Source-ID */
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VTD_FR_SM_PRE_ABS = 0x47, /* SCT.8 : PRE bit in a present SM CE is 0 */
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/* PASID directory entry access failure */
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VTD_FR_PASID_DIR_ACCESS_ERR = 0x50,
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/* The Present(P) field of pasid directory entry is 0 */
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@ -110,6 +110,7 @@ struct VTDAddressSpace {
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QLIST_ENTRY(VTDAddressSpace) next;
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/* Superset of notifier flags that this address space has */
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IOMMUNotifierFlag notifier_flags;
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IOMMUPRINotifier *pri_notifier;
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/*
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* @iova_tree traces mapped IOVA ranges.
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*
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