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i386/cpu: Add descriptor 0x49 for CPUID 0x2 encoding

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The legacy_l2_cache (2nd-level cache: 4 MByte, 16-way set associative,
64 byte line size) corresponds to descriptor 0x49, but at present
cpuid2_cache_descriptors doesn't support descriptor 0x49 because it has
multiple meanings.

The 0x49 is necessary when CPUID 0x2 and 0x4 leaves have the consistent
cache model, and use legacy_l2_cache as the default L2 cache.

Therefore, add descriptor 0x49 to represent general L2 cache.

Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Tested-by: Yi Lai <yi1.lai@intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20250711102143.1622339-3-zhao1.liu@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Zhao Liu 2025-07-11 18:21:27 +08:00 • committed by Paolo Bonzini
parent 1034b94fe9
commit 67d54014af
1 changed files with 12 additions and 1 deletions
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13
target/i386/cpu.c
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@ -129,7 +129,18 @@ struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = {
.associativity = 8, .line_size = 64, },
[0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB,
.associativity = 12, .line_size = 64, },
/* Descriptor 0x49 depends on CPU family/model, so it is not included */
/*
* Descriptor 0x49 has 2 cases:
* - 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size.
* - 3rd-level cache: 4MB, 16-way set associative, 64-byte line size
* (Intel Xeon processor MP, Family 0FH, Model 06H).
*
* When it represents L3, then it depends on CPU family/model. Fortunately,
* the legacy cache/CPU models don't have such special L3. So, just add it
* to represent the general L2 case.
*/
[0x49] = { .level = 2, .type = UNIFIED_CACHE, .size = 4 * MiB,
.associativity = 16, .line_size = 64, },
[0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
.associativity = 12, .line_size = 64, },
[0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,