wip! status register management
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fridtjof
parent
ecdcafd570
commit
7037504166
3 changed files with 127 additions and 12 deletions
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@ -59,7 +59,11 @@ static void cr16c_cpu_reset_hold(Object *obj, ResetType type)
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env->psr_f = 0;
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env->psr_l = 0;
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env->psr_c = 0;
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// TODO: Rest of flags from PSR once implemented
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env->psr_t = 0;
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env->psr_u = 0;
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env->psr_e = 0;
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env->psr_p = 0;
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env->psr_i = 0;
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env->pc = 0;
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}
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@ -97,11 +101,14 @@ static void cr16c_cpu_dump_state(CPUState *cs, FILE *f, int flags)
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qemu_fprintf(f, "SP: " TARGET_FMT_lx "\n", env->r[CR16C_REGNO_SP]);
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qemu_fprintf(f, "-- Flags --\n");
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qemu_fprintf(f, "N: %2d\n", env->psr_n);
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qemu_fprintf(f, "Z: %2d\n", env->psr_z);
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qemu_fprintf(f, "F: %2d\n", env->psr_f);
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qemu_fprintf(f, "L: %2d\n", env->psr_l);
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qemu_fprintf(f, "C: %2d\n", env->psr_c);
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qemu_fprintf(f, "PSR: %04x\n", cr16c_cpu_pack_psr(env));
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qemu_fprintf(f, ". I P E N Z F U L T C\n");
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qemu_fprintf(f, ". %d %d %d %d %d %d %d %d %d %d\n",
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env->psr_i, env->psr_p, env->psr_e, env->psr_n, env->psr_z, env->psr_f, env->psr_u, env->psr_l, env->psr_t, env->psr_c);
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qemu_fprintf(f, "CFG: %04x\n", cr16c_cpu_pack_cfg(env));
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qemu_fprintf(f, ". SR ED LIC IC DC\n");
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qemu_fprintf(f, ". %d %d %d %d %d\n",
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env->cfg_sr, env->cfg_ed, env->cfg_lic, env->cfg_ic, env->cfg_dc);
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qemu_fprintf(f, "\n");
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}
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@ -4,6 +4,36 @@
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#include "qemu/osdep.h"
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#include "cpu-qom.h"
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#include "exec/cpu-defs.h"
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#include "hw/registerfields.h"
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/* PSR define */
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REG16(PSR, 0)
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FIELD(PSR, C, 0, 1)
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FIELD(PSR, T, 1, 1)
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FIELD(PSR, L, 2, 1)
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FIELD(PSR, U, 3, 1)
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// bit 4 is reserved
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FIELD(PSR, F, 5, 1)
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FIELD(PSR, Z, 6, 1)
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FIELD(PSR, N, 7, 1)
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// bit 8 is reserved
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FIELD(PSR, E, 9, 1)
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FIELD(PSR, P, 10, 1)
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FIELD(PSR, I, 11, 1)
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// 12-15 are reserved as well
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/* CFG define */
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REG16(CFG, 0)
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// bit 0, 1 are fixed 0
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FIELD(CFG, DC, 2, 1)
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FIELD(CFG, LDC, 3, 1)
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FIELD(CFG, IC, 4, 1)
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FIELD(CFG, LIC, 5, 1)
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// bit 6, 7 are fixed 0
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FIELD(CFG, ED, 8, 1)
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FIELD(CFG, SR, 9, 1)
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// bit 10-15 are reserved
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#define CR16C_REG_COUNT 16
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#define CR16C_FIRST_32B_REG 12
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@ -25,11 +55,24 @@ typedef struct CPUArchState {
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uint32_t r[CR16C_REG_COUNT]; /* General purpose registers: 12x16-bit + 2x32-bit */
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uint32_t psr_n;
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uint32_t psr_z;
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uint32_t psr_f;
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uint32_t psr_l;
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uint32_t psr_c;
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uint32_t psr_n; // Negative bit
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uint32_t psr_z; // Zero bit
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uint32_t psr_f; // Flag bit
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uint32_t psr_l; // Low flag bit
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uint32_t psr_c; // Carry bit
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uint32_t psr_t; // Trace bit
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uint32_t psr_u; // User mode bit
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uint32_t psr_e; // local maskable interrupt Enable bit
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uint32_t psr_p; // trace trap Pending bit
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uint32_t psr_i; // global maskable Interrupt enable bit
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uint32_t cfg_dc; // Data Cache bit
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uint32_t cfg_ldc; // Lock Data Cache bit
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uint32_t cfg_ic; // Instruction Cache bit
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uint32_t cfg_lic; // Lock Instruction Cache bit
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uint32_t cfg_ed; // Extended Dispatch bit
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uint32_t cfg_sr; // Short Register bit
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} CPUCR16CState;
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struct ArchCPU {
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@ -63,4 +106,32 @@ void cr16c_translate_code(CPUState *cs, TranslationBlock *tb,
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void cr16c_restore_state_to_opc(CPUState *cpu, const TranslationBlock *tb,
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const uint64_t *data);
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static inline uint32_t cr16c_cpu_pack_psr(const CPUCR16CState *env)
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{
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uint32_t psr = 0;
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psr = FIELD_DP32(psr, PSR, C, env->psr_c);
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psr = FIELD_DP32(psr, PSR, T, env->psr_t);
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psr = FIELD_DP32(psr, PSR, L, env->psr_l);
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psr = FIELD_DP32(psr, PSR, U, env->psr_u);
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psr = FIELD_DP32(psr, PSR, N, env->psr_n);
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psr = FIELD_DP32(psr, PSR, Z, env->psr_z);
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psr = FIELD_DP32(psr, PSR, F, env->psr_f);
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psr = FIELD_DP32(psr, PSR, E, env->psr_e);
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psr = FIELD_DP32(psr, PSR, P, env->psr_p);
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psr = FIELD_DP32(psr, PSR, I, env->psr_i);
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return psr;
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}
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static inline uint32_t cr16c_cpu_pack_cfg(const CPUCR16CState *env)
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{
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uint32_t cfg = 0;
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cfg = FIELD_DP32(cfg, CFG, DC, env->cfg_dc);
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cfg = FIELD_DP32(cfg, CFG, LDC, env->cfg_ldc);
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cfg = FIELD_DP32(cfg, CFG, IC, env->cfg_ic);
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cfg = FIELD_DP32(cfg, CFG, LIC, env->cfg_lic);
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cfg = FIELD_DP32(cfg, CFG, ED, env->cfg_ed);
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cfg = FIELD_DP32(cfg, CFG, SR, env->cfg_sr);
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return cfg;
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}
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#endif // !QEMU_CR16C_CPU_H
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@ -66,12 +66,37 @@ typedef struct DisasContext {
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/* Registers */
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static TCGv pc;
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static TCGv pc; // 24 bit
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// ISPH/L (Interrupt Stack Pointer)
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// USPH/L (User Stack Pointer)
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// INTBASEH/L (Interrupt Base)
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// PSR 16
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// these flags are part of PSR
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static TCGv psr_n;
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static TCGv psr_z;
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static TCGv psr_f;
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static TCGv psr_l;
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static TCGv psr_c;
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static TCGv psr_t;
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static TCGv psr_u;
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static TCGv psr_e;
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static TCGv psr_p;
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static TCGv psr_i;
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// CFG
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// Most notably: SR bit "Short Register"
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// => switches to register pairings for reassembled code originally written for CR16B
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static TCGv cfg_dc;
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static TCGv cfg_ldc;
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static TCGv cfg_ic;
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static TCGv cfg_lic;
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static TCGv cfg_ed;
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static TCGv cfg_sr;
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// debug registers (optional) "depends on the configuration of the chip"
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/* General purpose registers, incl. RA and SP */
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static TCGv r[CR16C_REG_COUNT];
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@ -1646,6 +1671,18 @@ void cr16c_translate_init(void) {
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psr_f = tcg_global_mem_new_i32(tcg_env, offsetof(CPUCR16CState, psr_f), "psr_f");
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psr_l = tcg_global_mem_new_i32(tcg_env, offsetof(CPUCR16CState, psr_l), "psr_l");
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psr_c = tcg_global_mem_new_i32(tcg_env, offsetof(CPUCR16CState, psr_c), "psr_c");
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psr_t = tcg_global_mem_new_i32(tcg_env, offsetof(CPUCR16CState, psr_t), "psr_t");
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psr_u = tcg_global_mem_new_i32(tcg_env, offsetof(CPUCR16CState, psr_u), "psr_u");
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psr_e = tcg_global_mem_new_i32(tcg_env, offsetof(CPUCR16CState, psr_e), "psr_e");
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psr_p = tcg_global_mem_new_i32(tcg_env, offsetof(CPUCR16CState, psr_p), "psr_p");
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psr_i = tcg_global_mem_new_i32(tcg_env, offsetof(CPUCR16CState, psr_i), "psr_i");
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cfg_dc = tcg_global_mem_new_i32(tcg_env, offsetof(CPUCR16CState, cfg_dc), "cfg_dc");
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cfg_ldc = tcg_global_mem_new_i32(tcg_env, offsetof(CPUCR16CState, cfg_ldc), "cfg_ldc");
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cfg_ic = tcg_global_mem_new_i32(tcg_env, offsetof(CPUCR16CState, cfg_ic), "cfg_ic");
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cfg_lic = tcg_global_mem_new_i32(tcg_env, offsetof(CPUCR16CState, cfg_lic), "cfg_lic");
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cfg_ed = tcg_global_mem_new_i32(tcg_env, offsetof(CPUCR16CState, cfg_ed), "cfg_ed");
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cfg_sr = tcg_global_mem_new_i32(tcg_env, offsetof(CPUCR16CState, cfg_sr), "cfg_sr");
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}
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void cr16c_translate_code(CPUState *cs, TranslationBlock *tb,
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