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ppc/pnv: Introduce Power11 PowerNV machine

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The Powernv11 machine doesn't have XIVE & PHBs as of now

XIVE2 interface and PHB5 added in later patches to Powernv11 machine

Also add mention of Power11 to powernv documentation

Note: A difference from P10's and P11's machine_class_init is, in P11
different number of PHBs cannot be used on the command line, ie. the
following line does NOT exist in pnv_machine_power11_class_init, which
existed in case of Power10:

    machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB);

Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
Tested-by: Amit Machhiwal <amachhiw@linux.ibm.com>
Tested-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Link: https://lore.kernel.org/r/20250925173049.891406-3-adityag@linux.ibm.com
Message-ID: <20250925173049.891406-3-adityag@linux.ibm.com>
This commit is contained in:
Aditya Gupta 2025-09-25 23:00:43 +05:30 • committed by Harsh Prateek Bora
parent 98ee172538
commit 73a911e966
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GPG key ID: 4544E994F9D68FBB
2 changed files with 39 additions and 4 deletions
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9
docs/system/ppc/powernv.rst
View file

@ -1,5 +1,5 @@
PowerNV family boards (``powernv8``, ``powernv9``, ``powernv10``)
==================================================================
PowerNV family boards (``powernv8``, ``powernv9``, ``powernv10``, ``powernv11``)
================================================================================
PowerNV (as Non-Virtualized) is the "bare metal" platform using the
OPAL firmware. It runs Linux on IBM and OpenPOWER systems and it can
@ -15,11 +15,12 @@ beyond the scope of what QEMU addresses today.
Supported devices
-----------------
* Multi processor support for POWER8, POWER8NVL and POWER9.
* Multi processor support for POWER8, POWER8NVL, POWER9, Power10 and Power11.
* XSCOM, serial communication sideband bus to configure chiplets.
* Simple LPC Controller.
* Processor Service Interface (PSI) Controller.
* Interrupt Controller, XICS (POWER8) and XIVE (POWER9) and XIVE2 (Power10).
* Interrupt Controller, XICS (POWER8) and XIVE (POWER9) and XIVE2 (Power10 &
Power11).
* POWER8 PHB3 PCIe Host bridge and POWER9 PHB4 PCIe Host bridge.
* Simple OCC is an on-chip micro-controller used for power management tasks.
* iBT device to handle BMC communication, with the internal BMC simulator

34
hw/ppc/pnv.c
View file

@ -3235,6 +3235,35 @@ static void pnv_machine_p10_rainier_class_init(ObjectClass *oc,
pmc->i2c_init = pnv_rainier_i2c_init;
}
static void pnv_machine_power11_class_init(ObjectClass *oc, const void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
static const char compat[] = "qemu,powernv11\0ibm,powernv";
pmc->compat = compat;
pmc->compat_size = sizeof(compat);
pmc->max_smt_threads = 4;
pmc->has_lpar_per_thread = true;
pmc->quirk_tb_big_core = true;
pmc->dt_power_mgt = pnv_dt_power_mgt;
mc->desc = "IBM PowerNV (Non-Virtualized) Power11";
mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power11_v2.0");
object_class_property_add_bool(oc, "big-core",
pnv_machine_get_big_core,
pnv_machine_set_big_core);
object_class_property_set_description(oc, "big-core",
"Use big-core (aka fused-core) mode");
object_class_property_add_bool(oc, "lpar-per-core",
pnv_machine_get_lpar_per_core,
pnv_machine_set_lpar_per_core);
object_class_property_set_description(oc, "lpar-per-core",
"Use 1 LPAR per core mode");
}
static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg)
{
CPUPPCState *env = cpu_env(cs);
@ -3348,6 +3377,11 @@ static void pnv_machine_class_init(ObjectClass *oc, const void *data)
}
static const TypeInfo types[] = {
{
.name = MACHINE_TYPE_NAME("powernv11"),
.parent = TYPE_PNV_MACHINE,
.class_init = pnv_machine_power11_class_init,
},
{
.name = MACHINE_TYPE_NAME("powernv10-rainier"),
.parent = MACHINE_TYPE_NAME("powernv10"),