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target-arm queue:

Browse source 
* Fix VNCR fault detection logic
  * Fix A64 scalar SQSHRN and SQRSHRN
  * Fix incorrect aa64_tidcp1 feature check
  * hw/arm/virt.c: Remove newline from error_report() string
  * hw/arm/musicpal: Convert to qemu_add_kbd_event_handler()
  * hw/arm/allwinner-a10: Unconditionally map the USB Host controllers
  * hw/arm/nseries: Unconditionally map the TUSB6010 USB Host controller
  * hw/arm: Add EHCI/OHCI controllers to Allwinner R40 and Bananapi board
  * hw/arm: Add AHCI/SATA controller to Allwinner R40 and Bananapi board
  * hw/arm: Add watchdog timer to Allwinner H40 and Bananapi board
  * arm: various include header cleanups
  * cleanups to allow some files to be built only once
  * fsl-imx6ul: Add various missing unimplemented devices
  * docs/system/arm/virt.rst: Add note on CPU features off by default
  * hw/char/imx_serial: Implement receive FIFO and ageing timer
  * target/xtensa: fix OOB TLB entry access
  * bswap.h: Fix const_le64() macro
  * hw/arm: add PCIe to Freescale i.MX6
 -----BEGIN PGP SIGNATURE-----
 
 iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmWzwpsZHHBldGVyLm1h
 eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3oTVD/4jM7ttKlXxtWsJ/cKDL5Im
 uMmDECPrdK2qaNpONfV/YC3WadM6bSgB8OQd2YlI67DLgl3Hfaa+GnQsZhEgZ3lC
 VECOTg5OKwwJY+Ac86t1GJa483wDEQ6NL08oLN94n9Ub/9G0S3oWpmE4bgof7PzW
 rbLDDpKP+W5NfkqMfA5piV7N6mFHvg9wqFX//quqySIiu8NesKV9LmlP/FyNDU/s
 8ZeSqo/tq/IHr9IeYUtOoxVwYUOPuNKwD+vwy1taiXgjvVtq2URrCrlc4+KCWJsj
 VUBSXdY2boqK31KFZ9NP9kJhIS5gmzgnK8YrHX6sgSbh+IybZUv+y/4eSO/LDYIi
 r2VQF6oTtkmcIxUqAI6ZAehzZUIrB22QItUN8rg0slKBM8e/xHYaEBY8APKCLcvE
 h59DLq1rPZG3Aie/h3/RjTfT2kI83PiE1mDGbhKf9G8UfXHEH8Eabd0g66UWfzlK
 67o7bwwzwXgoGk2hgMY/yobB3pF5YCly/a3aN/aLEj387y8sNaT1ASR9LETj7TC3
 xOhn5f8G6OFKMVI3K8Sco8ILP15LELprAW2keL4jn+4y3Hfq5yC984yOSnlM0wug
 wWRvEr7U1ZiEbDaOvoa0beuYpeq1sm4OZ5yGJxGy3IuQ8pZpkHVTrBxw/NCNQnos
 fK5czVTGqvvmPXgPsQQm1A==
 =vYTy
 -----END PGP SIGNATURE-----

Merge tag 'pull-target-arm-20240126' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * Fix VNCR fault detection logic
 * Fix A64 scalar SQSHRN and SQRSHRN
 * Fix incorrect aa64_tidcp1 feature check
 * hw/arm/virt.c: Remove newline from error_report() string
 * hw/arm/musicpal: Convert to qemu_add_kbd_event_handler()
 * hw/arm/allwinner-a10: Unconditionally map the USB Host controllers
 * hw/arm/nseries: Unconditionally map the TUSB6010 USB Host controller
 * hw/arm: Add EHCI/OHCI controllers to Allwinner R40 and Bananapi board
 * hw/arm: Add AHCI/SATA controller to Allwinner R40 and Bananapi board
 * hw/arm: Add watchdog timer to Allwinner H40 and Bananapi board
 * arm: various include header cleanups
 * cleanups to allow some files to be built only once
 * fsl-imx6ul: Add various missing unimplemented devices
 * docs/system/arm/virt.rst: Add note on CPU features off by default
 * hw/char/imx_serial: Implement receive FIFO and ageing timer
 * target/xtensa: fix OOB TLB entry access
 * bswap.h: Fix const_le64() macro
 * hw/arm: add PCIe to Freescale i.MX6

# -----BEGIN PGP SIGNATURE-----
#
# iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmWzwpsZHHBldGVyLm1h
# eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3oTVD/4jM7ttKlXxtWsJ/cKDL5Im
# uMmDECPrdK2qaNpONfV/YC3WadM6bSgB8OQd2YlI67DLgl3Hfaa+GnQsZhEgZ3lC
# VECOTg5OKwwJY+Ac86t1GJa483wDEQ6NL08oLN94n9Ub/9G0S3oWpmE4bgof7PzW
# rbLDDpKP+W5NfkqMfA5piV7N6mFHvg9wqFX//quqySIiu8NesKV9LmlP/FyNDU/s
# 8ZeSqo/tq/IHr9IeYUtOoxVwYUOPuNKwD+vwy1taiXgjvVtq2URrCrlc4+KCWJsj
# VUBSXdY2boqK31KFZ9NP9kJhIS5gmzgnK8YrHX6sgSbh+IybZUv+y/4eSO/LDYIi
# r2VQF6oTtkmcIxUqAI6ZAehzZUIrB22QItUN8rg0slKBM8e/xHYaEBY8APKCLcvE
# h59DLq1rPZG3Aie/h3/RjTfT2kI83PiE1mDGbhKf9G8UfXHEH8Eabd0g66UWfzlK
# 67o7bwwzwXgoGk2hgMY/yobB3pF5YCly/a3aN/aLEj387y8sNaT1ASR9LETj7TC3
# xOhn5f8G6OFKMVI3K8Sco8ILP15LELprAW2keL4jn+4y3Hfq5yC984yOSnlM0wug
# wWRvEr7U1ZiEbDaOvoa0beuYpeq1sm4OZ5yGJxGy3IuQ8pZpkHVTrBxw/NCNQnos
# fK5czVTGqvvmPXgPsQQm1A==
# =vYTy
# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 26 Jan 2024 14:32:59 GMT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20240126' of https://git.linaro.org/people/pmaydell/qemu-arm: (36 commits)
  hw/arm: add PCIe to Freescale i.MX6
  target/arm: Fix incorrect aa64_tidcp1 feature check
  bswap.h: Fix const_le64() macro
  target/arm: Fix A64 scalar SQSHRN and SQRSHRN
  hw/char/imx_serial: Implement receive FIFO and ageing timer
  docs/system/arm/virt.rst: Add note on CPU features off by default
  fsl-imx6ul: Add various missing unimplemented devices
  hw/arm: Build various units only once
  target/arm: Move GTimer definitions to new 'gtimer.h' header
  target/arm: Move e2h_access() helper around
  target/arm: Move ARM_CPU_IRQ/FIQ definitions to 'cpu-qom.h' header
  hw/arm/armv7m: Make 'hw/intc/armv7m_nvic.h' a target agnostic header
  target/arm: Expose M-profile register bank index definitions
  hw/misc/xlnx-versal-crl: Build it only once
  hw/misc/xlnx-versal-crl: Include generic 'cpu-qom.h' instead of 'cpu.h'
  hw/cpu/a9mpcore: Build it only once
  target/arm: Declare ARM_CPU_TYPE_NAME/SUFFIX in 'cpu-qom.h'
  target/arm: Expose arm_cpu_mp_affinity() in 'multiprocessing.h' header
  target/arm: Create arm_cpu_mp_affinity
  target/arm: Rename arm_cpu_mp_affinity
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2024-01-26 18:16:34 +00:00
commit 7a1dc45af5
73 changed files with 597 additions and 261 deletions
Download patch file Download diff file Expand all files Collapse all files

15
include/hw/arm/allwinner-r40.h
View file

@ -22,6 +22,7 @@
#include "qom/object.h"
#include "hw/timer/allwinner-a10-pit.h"
#include "hw/ide/ahci.h"
#include "hw/intc/arm_gic.h"
#include "hw/sd/allwinner-sdhost.h"
#include "hw/misc/allwinner-r40-ccu.h"
@ -30,6 +31,9 @@
#include "hw/i2c/allwinner-i2c.h"
#include "hw/net/allwinner_emac.h"
#include "hw/net/allwinner-sun8i-emac.h"
#include "hw/usb/hcd-ohci.h"
#include "hw/usb/hcd-ehci.h"
#include "hw/watchdog/allwinner-wdt.h"
#include "target/arm/cpu.h"
#include "sysemu/block-backend.h"
@ -44,8 +48,14 @@ enum {
AW_R40_DEV_MMC1,
AW_R40_DEV_MMC2,
AW_R40_DEV_MMC3,
AW_R40_DEV_AHCI,
AW_R40_DEV_EHCI1,
AW_R40_DEV_OHCI1,
AW_R40_DEV_EHCI2,
AW_R40_DEV_OHCI2,
AW_R40_DEV_CCU,
AW_R40_DEV_PIT,
AW_R40_DEV_WDT,
AW_R40_DEV_UART0,
AW_R40_DEV_UART1,
AW_R40_DEV_UART2,
@ -88,6 +98,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(AwR40State, AW_R40)
* which are currently emulated by the R40 SoC code.
*/
#define AW_R40_NUM_MMCS 4
#define AW_R40_NUM_USB 2
#define AW_R40_NUM_UARTS 8
struct AwR40State {
@ -105,7 +116,11 @@ struct AwR40State {
const hwaddr *memmap;
AwSRAMCState sramc;
AwA10PITState timer;
AwWdtState wdt;
AllwinnerAHCIState sata;
AwSdHostState mmc[AW_R40_NUM_MMCS];
EHCISysBusState ehci[AW_R40_NUM_USB];
OHCISysBusState ohci[AW_R40_NUM_USB];
AwR40ClockCtlState ccu;
AwR40DramCtlState dramc;
AWI2CState i2c0;

44
include/hw/arm/fsl-imx6.h
View file

@ -32,6 +32,7 @@
#include "hw/net/imx_fec.h"
#include "hw/usb/chipidea.h"
#include "hw/usb/imx-usb-phy.h"
#include "hw/pci-host/designware.h"
#include "exec/memory.h"
#include "cpu.h"
#include "qom/object.h"
@ -55,27 +56,28 @@ struct FslIMX6State {
DeviceState parent_obj;
/*< public >*/
ARMCPU cpu[FSL_IMX6_NUM_CPUS];
A9MPPrivState a9mpcore;
IMX6CCMState ccm;
IMX6SRCState src;
IMX7SNVSState snvs;
IMXSerialState uart[FSL_IMX6_NUM_UARTS];
IMXGPTState gpt;
IMXEPITState epit[FSL_IMX6_NUM_EPITS];
IMXI2CState i2c[FSL_IMX6_NUM_I2CS];
IMXGPIOState gpio[FSL_IMX6_NUM_GPIOS];
SDHCIState esdhc[FSL_IMX6_NUM_ESDHCS];
IMXSPIState spi[FSL_IMX6_NUM_ECSPIS];
IMX2WdtState wdt[FSL_IMX6_NUM_WDTS];
IMXUSBPHYState usbphy[FSL_IMX6_NUM_USB_PHYS];
ChipideaState usb[FSL_IMX6_NUM_USBS];
IMXFECState eth;
MemoryRegion rom;
MemoryRegion caam;
MemoryRegion ocram;
MemoryRegion ocram_alias;
uint32_t phy_num;
ARMCPU cpu[FSL_IMX6_NUM_CPUS];
A9MPPrivState a9mpcore;
IMX6CCMState ccm;
IMX6SRCState src;
IMX7SNVSState snvs;
IMXSerialState uart[FSL_IMX6_NUM_UARTS];
IMXGPTState gpt;
IMXEPITState epit[FSL_IMX6_NUM_EPITS];
IMXI2CState i2c[FSL_IMX6_NUM_I2CS];
IMXGPIOState gpio[FSL_IMX6_NUM_GPIOS];
SDHCIState esdhc[FSL_IMX6_NUM_ESDHCS];
IMXSPIState spi[FSL_IMX6_NUM_ECSPIS];
IMX2WdtState wdt[FSL_IMX6_NUM_WDTS];
IMXUSBPHYState usbphy[FSL_IMX6_NUM_USB_PHYS];
ChipideaState usb[FSL_IMX6_NUM_USBS];
IMXFECState eth;
DesignwarePCIEHost pcie;
MemoryRegion rom;
MemoryRegion caam;
MemoryRegion ocram;
MemoryRegion ocram_alias;
uint32_t phy_num;
};

2
include/hw/arm/fsl-imx6ul.h
View file

@ -182,6 +182,8 @@ enum FslIMX6ULMemoryMap {
FSL_IMX6UL_ENET1_ADDR = 0x02188000,
FSL_IMX6UL_USBO2_USBMISC_ADDR = 0x02184800,
FSL_IMX6UL_USBO2_USBMISC_SIZE = 0x200,
FSL_IMX6UL_USBO2_USB1_ADDR = 0x02184000,
FSL_IMX6UL_USBO2_USB2_ADDR = 0x02184200,

1
include/hw/arm/xlnx-versal.h
View file

@ -34,6 +34,7 @@
#include "hw/net/xlnx-versal-canfd.h"
#include "hw/misc/xlnx-versal-cfu.h"
#include "hw/misc/xlnx-versal-cframe-reg.h"
#include "target/arm/cpu.h"
#define TYPE_XLNX_VERSAL "xlnx-versal"
OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)

20
include/hw/char/imx_serial.h
View file

@ -21,12 +21,16 @@
#include "hw/sysbus.h"
#include "chardev/char-fe.h"
#include "qom/object.h"
#include "qemu/fifo32.h"
#define TYPE_IMX_SERIAL "imx.serial"
OBJECT_DECLARE_SIMPLE_TYPE(IMXSerialState, IMX_SERIAL)
#define FIFO_SIZE 32
#define URXD_CHARRDY (1<<15) /* character read is valid */
#define URXD_ERR (1<<14) /* Character has error */
#define URXD_OVRRUN (1<<13) /* 32nd character in RX FIFO */
#define URXD_FRMERR (1<<12) /* Character has frame error */
#define URXD_BRK (1<<11) /* Break received */
@ -65,11 +69,13 @@ OBJECT_DECLARE_SIMPLE_TYPE(IMXSerialState, IMX_SERIAL)
#define UCR1_TXMPTYEN (1<<6) /* Tx Empty Interrupt Enable */
#define UCR1_UARTEN (1<<0) /* UART Enable */
#define UCR2_ATEN (1<<3) /* Ageing Timer Enable */
#define UCR2_TXEN (1<<2) /* Transmitter enable */
#define UCR2_RXEN (1<<1) /* Receiver enable */
#define UCR2_SRST (1<<0) /* Reset complete */
#define UCR4_DREN BIT(0) /* Receive Data Ready interrupt enable */
#define UCR4_OREN BIT(1) /* Overrun interrupt enable */
#define UCR4_TCEN BIT(3) /* TX complete interrupt enable */
#define UCR4_WKEN BIT(7) /* WAKE interrupt enable */
@ -78,13 +84,25 @@ OBJECT_DECLARE_SIMPLE_TYPE(IMXSerialState, IMX_SERIAL)
#define UTS1_TXFULL (1<<4)
#define UTS1_RXFULL (1<<3)
#define TL_MASK 0x3f
/* Bit time in nanoseconds assuming maximum baud rate of 115200 */
#define BIT_TIME_NS 8681
/* Assume 8 bits per character */
#define NUM_BITS 8
/* Ageing timer triggers after 8 characters */
#define AGE_DURATION_NS (8 * NUM_BITS * BIT_TIME_NS)
struct IMXSerialState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion iomem;
int32_t readbuff;
QEMUTimer ageing_timer;
Fifo32 rx_fifo;
uint32_t usr1;
uint32_t usr2;

2
include/hw/intc/armv7m_nvic.h
View file

@ -10,7 +10,7 @@
#ifndef HW_ARM_ARMV7M_NVIC_H
#define HW_ARM_ARMV7M_NVIC_H
#include "target/arm/cpu.h"
#include "target/arm/cpu-qom.h"
#include "hw/sysbus.h"
#include "hw/timer/armv7m_systick.h"
#include "qom/object.h"

2
include/hw/misc/xlnx-versal-crl.h
View file

@ -11,7 +11,7 @@
#include "hw/sysbus.h"
#include "hw/register.h"
#include "target/arm/cpu.h"
#include "target/arm/cpu-qom.h"
#define TYPE_XLNX_VERSAL_CRL "xlnx-versal-crl"
OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCRL, XLNX_VERSAL_CRL)

16
include/qemu/bswap.h
View file

@ -145,14 +145,14 @@ CPU_CONVERT(le, 64, uint64_t)
*/
#if HOST_BIG_ENDIAN
# define const_le64(_x) \
((((_x) & 0x00000000000000ffU) << 56) | \
(((_x) & 0x000000000000ff00U) << 40) | \
(((_x) & 0x0000000000ff0000U) << 24) | \
(((_x) & 0x00000000ff000000U) << 8) | \
(((_x) & 0x000000ff00000000U) >> 8) | \
(((_x) & 0x0000ff0000000000U) >> 24) | \
(((_x) & 0x00ff000000000000U) >> 40) | \
(((_x) & 0xff00000000000000U) >> 56))
((((_x) & 0x00000000000000ffULL) << 56) | \
(((_x) & 0x000000000000ff00ULL) << 40) | \
(((_x) & 0x0000000000ff0000ULL) << 24) | \
(((_x) & 0x00000000ff000000ULL) << 8) | \
(((_x) & 0x000000ff00000000ULL) >> 8) | \
(((_x) & 0x0000ff0000000000ULL) >> 24) | \
(((_x) & 0x00ff000000000000ULL) >> 40) | \
(((_x) & 0xff00000000000000ULL) >> 56))
# define const_le32(_x) \
((((_x) & 0x000000ffU) << 24) | \
(((_x) & 0x0000ff00U) << 8) | \