fridtjof/qemu-cr16
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

loongarch queue

Browse source 
-----BEGIN PGP SIGNATURE-----
 
 iHUEABYKAB0WIQQNhkKjomWfgLCz0aQfewwSUazn0QUCaO8QRQAKCRAfewwSUazn
 0UxeAQCM8zwwTBnAWbDJpxPWTVD5yz+Bv2YP+IbDc24BkzEvJwD/Z+5u+gEuBtum
 U8tTU/huVLezwpbwqgpTAYI2wJAOygw=
 =XZMy
 -----END PGP SIGNATURE-----

Merge tag 'pull-loongarch-20251015' of https://github.com/bibo-mao/qemu into staging

loongarch queue

# -----BEGIN PGP SIGNATURE-----
#
# iHUEABYKAB0WIQQNhkKjomWfgLCz0aQfewwSUazn0QUCaO8QRQAKCRAfewwSUazn
# 0UxeAQCM8zwwTBnAWbDJpxPWTVD5yz+Bv2YP+IbDc24BkzEvJwD/Z+5u+gEuBtum
# U8tTU/huVLezwpbwqgpTAYI2wJAOygw=
# =XZMy
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 14 Oct 2025 08:08:53 PM PDT
# gpg:                using EDDSA key 0D8642A3A2659F80B0B3D1A41F7B0C1251ACE7D1
# gpg: Good signature from "bibo mao <maobibo@loongson.cn>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 7044 3A00 19C0 E97A 31C7  13C4 8E86 8FB7 A176 9D4C
#      Subkey fingerprint: 0D86 42A3 A265 9F80 B0B3  D1A4 1F7B 0C12 51AC E7D1

* tag 'pull-loongarch-20251015' of https://github.com/bibo-mao/qemu:
  hw/loongarch/virt: Sort order by hardware device base address
  hw/loongarch/virt: Remove header file ls7a.h
  target/loongarch: Skip global TLB when calculating replaced TLB
  target/loongarch: Add missing TLB flush with different asid

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2025-10-15 14:49:51 -07:00
commit 8109ebdb95
9 changed files with 70 additions and 75 deletions
Download patch file Download diff file Expand all files Collapse all files

1
MAINTAINERS
View file

@ -1308,7 +1308,6 @@ F: include/hw/intc/loongarch_*.h
F: include/hw/intc/loongson_ipi_common.h
F: hw/intc/loongarch_*.c
F: hw/intc/loongson_ipi_common.c
F: include/hw/pci-host/ls7a.h
F: hw/rtc/ls7a_rtc.c
F: gdb-xml/loongarch*.xml

1
hw/intc/loongarch_pic_kvm.c
View file

@ -10,7 +10,6 @@
#include "hw/boards.h"
#include "hw/intc/loongarch_pch_pic.h"
#include "hw/loongarch/virt.h"
#include "hw/pci-host/ls7a.h"
#include "system/kvm.h"
static void kvm_pch_pic_access_reg(int fd, uint64_t addr, void *val, bool write)

1
hw/loongarch/virt-acpi-build.c
View file

@ -21,7 +21,6 @@
#include "system/reset.h"
/* Supported chipsets: */
#include "hw/pci-host/ls7a.h"
#include "hw/loongarch/virt.h"
#include "hw/acpi/utils.h"

1
hw/loongarch/virt-fdt-build.c
View file

@ -12,7 +12,6 @@
#include "hw/loader.h"
#include "hw/loongarch/virt.h"
#include "hw/pci-host/gpex.h"
#include "hw/pci-host/ls7a.h"
#include "system/device_tree.h"
#include "system/reset.h"
#include "target/loongarch/cpu.h"

3
hw/loongarch/virt.c
View file

@ -29,7 +29,6 @@
#include "hw/intc/loongarch_pch_pic.h"
#include "hw/intc/loongarch_pch_msi.h"
#include "hw/intc/loongarch_dintc.h"
#include "hw/pci-host/ls7a.h"
#include "hw/pci-host/gpex.h"
#include "hw/misc/unimp.h"
#include "hw/loongarch/fw_cfg.h"
@ -521,7 +520,7 @@ static void virt_irq_init(LoongArchVirtMachineState *lvms)
}
/* PCH_PIC memory region */
memory_region_add_subregion(get_system_memory(), VIRT_IOAPIC_REG_BASE,
memory_region_add_subregion(get_system_memory(), VIRT_PCH_REG_BASE,
sysbus_mmio_get_region(SYS_BUS_DEVICE(pch_pic), 0));
/* Connect pch_pic irqs to extioi */

2
include/hw/intc/loongarch_pic_common.h
View file

@ -7,7 +7,7 @@
#ifndef HW_LOONGARCH_PIC_COMMON_H
#define HW_LOONGARCH_PIC_COMMON_H
#include "hw/pci-host/ls7a.h"
#include "hw/loongarch/virt.h"
#include "hw/sysbus.h"
#define PCH_PIC_INT_ID 0x00

75
include/hw/loongarch/virt.h
View file

@ -13,49 +13,84 @@
#include "hw/block/flash.h"
#include "hw/loongarch/boot.h"
#define IOCSRF_TEMP 0
#define IOCSRF_NODECNT 1
#define IOCSRF_MSI 2
#define IOCSRF_EXTIOI 3
#define IOCSRF_CSRIPI 4
#define IOCSRF_FREQCSR 5
#define IOCSRF_FREQSCALE 6
#define IOCSRF_DVFSV1 7
#define IOCSRF_GMOD 9
#define IOCSRF_VM 11
#define IOCSRF_DMSI 15
/* IOCSR region */
#define VERSION_REG 0x0
#define FEATURE_REG 0x8
#define IOCSRF_TEMP 0
#define IOCSRF_NODECNT 1
#define IOCSRF_MSI 2
#define IOCSRF_EXTIOI 3
#define IOCSRF_CSRIPI 4
#define IOCSRF_FREQCSR 5
#define IOCSRF_FREQSCALE 6
#define IOCSRF_DVFSV1 7
#define IOCSRF_GMOD 9
#define IOCSRF_VM 11
#define IOCSRF_DMSI 15
#define VENDOR_REG 0x10
#define CPUNAME_REG 0x20
#define MISC_FUNC_REG 0x420
#define IOCSRM_EXTIOI_EN 48
#define IOCSRM_EXTIOI_INT_ENCODE 49
#define IOCSRM_DMSI_EN 51
#define IOCSRM_EXTIOI_EN 48
#define IOCSRM_EXTIOI_INT_ENCODE 49
#define IOCSRM_DMSI_EN 51
#define LOONGARCH_MAX_CPUS 256
#define VIRT_FWCFG_BASE 0x1e020000UL
/* MMIO memory region */
#define VIRT_PCH_REG_BASE 0x10000000UL
#define VIRT_PCH_REG_SIZE 0x400
#define VIRT_RTC_REG_BASE 0x100d0100UL
#define VIRT_RTC_LEN 0x100
#define VIRT_PLATFORM_BUS_BASEADDRESS 0x16000000UL
#define VIRT_PLATFORM_BUS_SIZE 0x02000000
#define VIRT_PCI_IO_BASE 0x18004000UL
#define VIRT_PCI_IO_OFFSET 0x4000
#define VIRT_PCI_IO_SIZE 0xC000
#define VIRT_BIOS_BASE 0x1c000000UL
#define VIRT_BIOS_SIZE (16 * MiB)
#define VIRT_BIOS_SIZE 0x01000000UL
#define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
#define VIRT_FLASH0_BASE VIRT_BIOS_BASE
#define VIRT_FLASH0_SIZE VIRT_BIOS_SIZE
#define VIRT_FLASH1_BASE 0x1d000000UL
#define VIRT_FLASH1_SIZE (16 * MiB)
#define VIRT_FLASH1_SIZE 0x01000000UL
#define VIRT_FWCFG_BASE 0x1e020000UL
#define VIRT_UART_BASE 0x1fe001e0UL
#define VIRT_UART_SIZE 0x100
#define VIRT_PCI_CFG_BASE 0x20000000UL
#define VIRT_PCI_CFG_SIZE 0x08000000UL
#define VIRT_DINTC_BASE 0x2FE00000UL
#define VIRT_DINTC_SIZE 0x00100000UL
#define VIRT_PCH_MSI_ADDR_LOW 0x2FF00000UL
#define VIRT_PCH_MSI_SIZE 0x8
#define VIRT_PCI_MEM_BASE 0x40000000UL
#define VIRT_PCI_MEM_SIZE 0x40000000UL
#define VIRT_LOWMEM_BASE 0
#define VIRT_LOWMEM_SIZE 0x10000000
#define FDT_BASE 0x100000
#define VIRT_HIGHMEM_BASE 0x80000000
#define VIRT_GED_EVT_ADDR 0x100e0000
#define VIRT_GED_MEM_ADDR QEMU_ALIGN_UP(VIRT_GED_EVT_ADDR + ACPI_GED_EVT_SEL_LEN, 4)
#define VIRT_GED_REG_ADDR QEMU_ALIGN_UP(VIRT_GED_MEM_ADDR + MEMORY_HOTPLUG_IO_LEN, 4)
#define VIRT_GED_CPUHP_ADDR QEMU_ALIGN_UP(VIRT_GED_REG_ADDR + ACPI_GED_REG_COUNT, 4)
#define COMMAND_LINE_SIZE 512
/*
* GSI_BASE is hard-coded with 64 in linux kernel, else kernel fails to boot
* 0 - 15 GSI for ISA devices even if there is no ISA devices
* 16 - 63 GSI for CPU devices such as timers/perf monitor etc
* 64 - GSI for external devices
*/
#define VIRT_PCH_PIC_IRQ_NUM 32
#define VIRT_GSI_BASE 64
#define VIRT_DEVICE_IRQS 16
#define VIRT_UART_IRQ (VIRT_GSI_BASE + 2)
#define VIRT_UART_COUNT 4
#define VIRT_RTC_IRQ (VIRT_GSI_BASE + 6)
#define VIRT_SCI_IRQ (VIRT_GSI_BASE + 7)
#define VIRT_PLATFORM_BUS_IRQ (VIRT_GSI_BASE + 8)
#define VIRT_PLATFORM_BUS_NUM_IRQS 2
#define FDT_BASE 0x100000
#define COMMAND_LINE_SIZE 512
struct LoongArchVirtMachineState {
/*< private >*/

39
include/hw/pci-host/ls7a.h
View file

@ -13,43 +13,4 @@
#include "qemu/range.h"
#include "qom/object.h"
#define VIRT_PCI_MEM_BASE 0x40000000UL
#define VIRT_PCI_MEM_SIZE 0x40000000UL
#define VIRT_PCI_IO_OFFSET 0x4000
#define VIRT_PCI_CFG_BASE 0x20000000
#define VIRT_PCI_CFG_SIZE 0x08000000
#define VIRT_PCI_IO_BASE 0x18004000UL
#define VIRT_PCI_IO_SIZE 0xC000
#define VIRT_PCH_REG_BASE 0x10000000UL
#define VIRT_IOAPIC_REG_BASE (VIRT_PCH_REG_BASE)
#define VIRT_PCH_MSI_ADDR_LOW 0x2FF00000UL
#define VIRT_DINTC_SIZE 0x100000UL
#define VIRT_DINTC_BASE 0x2FE00000UL
#define VIRT_PCH_REG_SIZE 0x400
#define VIRT_PCH_MSI_SIZE 0x8
/*
* GSI_BASE is hard-coded with 64 in linux kernel, else kernel fails to boot
* 0 - 15 GSI for ISA devices even if there is no ISA devices
* 16 - 63 GSI for CPU devices such as timers/perf monitor etc
* 64 - GSI for external devices
*/
#define VIRT_PCH_PIC_IRQ_NUM 32
#define VIRT_GSI_BASE 64
#define VIRT_DEVICE_IRQS 16
#define VIRT_UART_COUNT 4
#define VIRT_UART_IRQ (VIRT_GSI_BASE + 2)
#define VIRT_UART_BASE 0x1fe001e0
#define VIRT_UART_SIZE 0x100
#define VIRT_RTC_IRQ (VIRT_GSI_BASE + 6)
#define VIRT_MISC_REG_BASE (VIRT_PCH_REG_BASE + 0x00080000)
#define VIRT_RTC_REG_BASE (VIRT_MISC_REG_BASE + 0x00050100)
#define VIRT_RTC_LEN 0x100
#define VIRT_SCI_IRQ (VIRT_GSI_BASE + 7)
#define VIRT_PLATFORM_BUS_BASEADDRESS 0x16000000
#define VIRT_PLATFORM_BUS_SIZE 0x2000000
#define VIRT_PLATFORM_BUS_NUM_IRQS 2
#define VIRT_PLATFORM_BUS_IRQ (VIRT_GSI_BASE + 8)
#endif

22
target/loongarch/tcg/tlb_helper.c
View file

@ -117,13 +117,7 @@ static void invalidate_tlb_entry(CPULoongArchState *env, int index)
uint8_t tlb_v0 = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, V);
uint8_t tlb_v1 = FIELD_EX64(tlb->tlb_entry1, TLBENTRY, V);
uint64_t tlb_vppn = FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN);
uint8_t tlb_e = FIELD_EX64(tlb->tlb_misc, TLB_MISC, E);
if (!tlb_e) {
return;
}
tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 0);
tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
pagesize = MAKE_64BIT_MASK(tlb_ps, 1);
mask = MAKE_64BIT_MASK(0, tlb_ps + 1);
@ -145,11 +139,19 @@ static void invalidate_tlb(CPULoongArchState *env, int index)
{
LoongArchTLB *tlb;
uint16_t csr_asid, tlb_asid, tlb_g;
uint8_t tlb_e;
csr_asid = FIELD_EX64(env->CSR_ASID, CSR_ASID, ASID);
tlb = &env->tlb[index];
tlb_e = FIELD_EX64(tlb->tlb_misc, TLB_MISC, E);
if (!tlb_e) {
return;
}
tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 0);
tlb_asid = FIELD_EX64(tlb->tlb_misc, TLB_MISC, ASID);
tlb_g = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, G);
/* QEMU TLB is flushed when asid is changed */
if (tlb_g == 0 && tlb_asid != csr_asid) {
return;
}
@ -369,7 +371,7 @@ void helper_tlbfill(CPULoongArchState *env)
uint16_t pagesize, stlb_ps;
uint16_t asid, tlb_asid;
LoongArchTLB *tlb;
uint8_t tlb_e;
uint8_t tlb_e, tlb_g;
if (FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) {
entryhi = env->CSR_TLBREHI;
@ -398,7 +400,8 @@ void helper_tlbfill(CPULoongArchState *env)
}
tlb_asid = FIELD_EX64(tlb->tlb_misc, TLB_MISC, ASID);
if (asid != tlb_asid) {
tlb_g = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, G);
if (tlb_g == 0 && asid != tlb_asid) {
set = i;
}
}
@ -421,7 +424,8 @@ void helper_tlbfill(CPULoongArchState *env)
}
tlb_asid = FIELD_EX64(tlb->tlb_misc, TLB_MISC, ASID);
if (asid != tlb_asid) {
tlb_g = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, G);
if (tlb_g == 0 && asid != tlb_asid) {
index = i;
}
}