hw/arm/xlnx-versal-virt: rename the machine to amd-versal-virt

To align with current branding and ensure coherency with the upcoming
versal2 machine, rename the xlnx-versal-virt machine to amd-versal-virt.
Keep an alias of the old name to the new one for command-line backward
compatibility.

Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20250926070806.292065-42-luc.michel@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Luc Michel 2025-09-26 09:07:59 +02:00 committed by Peter Maydell
parent 8cd160dccf
commit 84a759c3d2
3 changed files with 25 additions and 18 deletions

View file

@ -1,19 +1,23 @@
Xilinx Versal Virt (``xlnx-versal-virt``)
=========================================
AMD Versal Virt (``amd-versal-virt``)
=====================================
Xilinx Versal is a family of heterogeneous multi-core SoCs
AMD Versal is a family of heterogeneous multi-core SoCs
(System on Chip) that combine traditional hardened CPUs and I/O
peripherals in a Processing System (PS) with runtime programmable
FPGA logic (PL) and an Artificial Intelligence Engine (AIE).
QEMU implements the Versal Series variant of Versal SoCs, with the
``amd-versal-virt`` machine. The alias ``xlnx-versal-virt`` is kept for
backward compatibility.
More details here:
https://www.xilinx.com/products/silicon-devices/acap/versal.html
https://www.amd.com/en/products/adaptive-socs-and-fpgas/versal.html
The family of Versal SoCs share a single architecture but come in
different parts with different speed grades, amounts of PL and
other differences.
The Xilinx Versal Virt board in QEMU is a model of a virtual board
The AMD Versal Virt board in QEMU is a model of a virtual board
(does not exist in reality) with a virtual Versal SoC without I/O
limitations. Currently, we support the following cores and devices:
@ -74,7 +78,7 @@ Direct Linux boot of a generic ARM64 upstream Linux kernel:
.. code-block:: bash
$ qemu-system-aarch64 -M xlnx-versal-virt -m 2G \
$ qemu-system-aarch64 -M amd-versal-virt -m 2G \
-serial mon:stdio -display none \
-kernel arch/arm64/boot/Image \
-nic user -nic user \
@ -87,7 +91,7 @@ Direct Linux boot of PetaLinux 2019.2:
.. code-block:: bash
$ qemu-system-aarch64 -M xlnx-versal-virt -m 2G \
$ qemu-system-aarch64 -M amd-versal-virt -m 2G \
-serial mon:stdio -display none \
-kernel petalinux-v2019.2/Image \
-append "rdinit=/sbin/init console=ttyAMA0,115200n8 earlycon=pl011,mmio,0xFF000000,115200n8" \
@ -100,7 +104,7 @@ version of ATF tries to configure the CCI which we don't model) and U-boot:
.. code-block:: bash
$ qemu-system-aarch64 -M xlnx-versal-virt -m 2G \
$ qemu-system-aarch64 -M amd-versal-virt -m 2G \
-serial stdio -display none \
-device loader,file=petalinux-v2018.3/bl31.elf,cpu-num=0 \
-device loader,file=petalinux-v2019.2/u-boot.elf \
@ -125,7 +129,7 @@ Boot Linux as DOM0 on Xen via U-Boot:
.. code-block:: bash
$ qemu-system-aarch64 -M xlnx-versal-virt -m 4G \
$ qemu-system-aarch64 -M amd-versal-virt -m 4G \
-serial stdio -display none \
-device loader,file=petalinux-v2019.2/u-boot.elf,cpu-num=0 \
-device loader,addr=0x30000000,file=linux/2018-04-24/xen \
@ -153,7 +157,7 @@ Boot Linux as Dom0 on Xen via ARM Trusted Firmware and U-Boot:
.. code-block:: bash
$ qemu-system-aarch64 -M xlnx-versal-virt -m 4G \
$ qemu-system-aarch64 -M amd-versal-virt -m 4G \
-serial stdio -display none \
-device loader,file=petalinux-v2018.3/bl31.elf,cpu-num=0 \
-device loader,file=petalinux-v2019.2/u-boot.elf \
@ -227,7 +231,7 @@ To use a different index value, N, from default of 1, add:
is highly recommended (albeit with usage complexity).
Better yet, do not use actual product data when running guest image
on this Xilinx Versal Virt board.
on this AMD Versal Virt board.
Using CANFDs for Versal Virt
""""""""""""""""""""""""""""

View file

@ -1,5 +1,5 @@
/*
* Xilinx Versal Virtual board.
* AMD/Xilinx Versal Virtual board.
*
* Copyright (c) 2018 Xilinx Inc.
* Copyright (c) 2025 Advanced Micro Devices, Inc.
@ -26,7 +26,7 @@
#include "qom/object.h"
#include "target/arm/cpu.h"
#define TYPE_XLNX_VERSAL_VIRT_MACHINE MACHINE_TYPE_NAME("xlnx-versal-virt")
#define TYPE_XLNX_VERSAL_VIRT_MACHINE MACHINE_TYPE_NAME("amd-versal-virt")
OBJECT_DECLARE_SIMPLE_TYPE(VersalVirt, XLNX_VERSAL_VIRT_MACHINE)
#define XLNX_VERSAL_NUM_OSPI_FLASH 4
@ -55,6 +55,7 @@ struct VersalVirt {
static void fdt_create(VersalVirt *s)
{
MachineClass *mc = MACHINE_GET_CLASS(s);
const char versal_compat[] = "amd-versal-virt\0xlnx-versal-virt";
s->fdt = create_device_tree(&s->fdt_size);
if (!s->fdt) {
@ -72,7 +73,8 @@ static void fdt_create(VersalVirt *s)
/* Header */
qemu_fdt_setprop_string(s->fdt, "/", "model", mc->desc);
qemu_fdt_setprop_string(s->fdt, "/", "compatible", "xlnx-versal-virt");
qemu_fdt_setprop(s->fdt, "/", "compatible", versal_compat,
sizeof(versal_compat));
}
static void fdt_add_clk_node(VersalVirt *s, const char *name,
@ -348,7 +350,8 @@ static void versal_virt_machine_class_init(ObjectClass *oc, const void *data)
MachineClass *mc = MACHINE_CLASS(oc);
int num_cpu = versal_get_num_cpu(VERSAL_VER_VERSAL);
mc->desc = "Xilinx Versal Virtual development board";
mc->desc = "AMD Versal Virtual development board";
mc->alias = "xlnx-versal-virt";
mc->init = versal_virt_init;
mc->min_cpus = num_cpu;
mc->max_cpus = num_cpu;

View file

@ -6,7 +6,7 @@
from qemu_test import LinuxKernelTest, Asset
class XlnxVersalVirtMachine(LinuxKernelTest):
class AmdVersalVirtMachine(LinuxKernelTest):
ASSET_KERNEL = Asset(
('http://ports.ubuntu.com/ubuntu-ports/dists/bionic-updates/main/'
@ -20,8 +20,8 @@ class XlnxVersalVirtMachine(LinuxKernelTest):
'/ubuntu-installer/arm64/initrd.gz'),
'e7a5e716b6f516d8be315c06e7331aaf16994fe4222e0e7cfb34bc015698929e')
def test_aarch64_xlnx_versal_virt(self):
self.set_machine('xlnx-versal-virt')
def test_aarch64_amd_versal_virt(self):
self.set_machine('amd-versal-virt')
kernel_path = self.ASSET_KERNEL.fetch()
initrd_path = self.ASSET_INITRD.fetch()