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target/riscv: Replace HOST_BIG_ENDIAN #ifdef with if() check

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Replace preprocessor-time #ifdef with a compile-time check
to ensure all code paths are built and tested. This reduces
build-time configuration complexity and simplifies code
maintainability.

No functional change intended.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20251010134226.72221-14-philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2025-10-10 14:46:36 +02:00
parent 89e1cd7363
commit 886b0cea41
2 changed files with 24 additions and 24 deletions
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16
target/riscv/insn_trans/trans_rvv.c.inc
View file

@ -3351,19 +3351,19 @@ static void load_element(TCGv_i64 dest, TCGv_ptr base,
/* offset of the idx element with base register r */
static uint32_t endian_ofs(DisasContext *s, int r, int idx)
{
#if HOST_BIG_ENDIAN
return vreg_ofs(s, r) + ((idx ^ (7 >> s->sew)) << s->sew);
#else
return vreg_ofs(s, r) + (idx << s->sew);
#endif
if (HOST_BIG_ENDIAN) {
return vreg_ofs(s, r) + ((idx ^ (7 >> s->sew)) << s->sew);
} else {
return vreg_ofs(s, r) + (idx << s->sew);
}
}
/* adjust the index according to the endian */
static void endian_adjust(TCGv_i32 ofs, int sew)
{
#if HOST_BIG_ENDIAN
tcg_gen_xori_i32(ofs, ofs, 7 >> sew);
#endif
if (HOST_BIG_ENDIAN) {
tcg_gen_xori_i32(ofs, ofs, 7 >> sew);
}
}
/* Load idx >= VLMAX ? 0 : vreg[idx] */

32
target/riscv/vector_helper.c
View file

@ -235,26 +235,26 @@ vext_continuous_ldst_host(CPURISCVState *env, vext_ldst_elem_fn_host *ldst_host,
void *vd, uint32_t evl, uint32_t reg_start, void *host,
uint32_t esz, bool is_load)
{
#if HOST_BIG_ENDIAN
for (; reg_start < evl; reg_start++, host += esz) {
ldst_host(vd, reg_start, host);
}
#else
if (esz == 1) {
uint32_t byte_offset = reg_start * esz;
uint32_t size = (evl - reg_start) * esz;
if (is_load) {
memcpy(vd + byte_offset, host, size);
} else {
memcpy(host, vd + byte_offset, size);
}
} else {
if (HOST_BIG_ENDIAN) {
for (; reg_start < evl; reg_start++, host += esz) {
ldst_host(vd, reg_start, host);
}
} else {
if (esz == 1) {
uint32_t byte_offset = reg_start * esz;
uint32_t size = (evl - reg_start) * esz;
if (is_load) {
memcpy(vd + byte_offset, host, size);
} else {
memcpy(host, vd + byte_offset, size);
}
} else {
for (; reg_start < evl; reg_start++, host += esz) {
ldst_host(vd, reg_start, host);
}
}
}
#endif
}
static void vext_set_tail_elems_1s(target_ulong vl, void *vd,