diff --git a/target/cr16c/insn.decode b/target/cr16c/insn.decode
index 39863de46d..38d87efc4e 100644
--- a/target/cr16c/insn.decode
+++ b/target/cr16c/insn.decode
@@ -1,7 +1,7 @@
 %param84_dest  56:4 48:4
 
 @escape2_opc      .... .... .... ....  .... rd:4 rs1:4 rs2:4
-@escape2_res      .... .... .... ....  .... .... rs:4  rd:4
+@escape2_dc       .... .... .... ....  .... .... rs:4  rd:4
 
 @param4           .... .... .... imm:4
 @param4_20        .... .... rd:4 imm:20
@@ -62,13 +62,12 @@ SUBCB_imm4_16  0011 1100 .... ....                                            @p
 SUBCB_reg      0011 1101 .... ....                                            @param44
 SUBCW_imm4_16  0011 1110 .... ....                                            @param44_imm
 SUBCW_reg      0011 1111 .... ....                                            @param44
-SUBD_reg       0000 0000 0001 0100  1100 0000 .... ....                       @escape2_res
+SUBD_reg       0000 0000 0001 0100  1100 0000 .... ....                       @escape2_dc
 SUBD_imm32     0000 0000 0011 ....  .... .... .... ....  .... .... .... ....  @param4_32
 SUBW_imm4_16   0011 1010 .... ....                                            @param44_imm
 SUBW_reg       0011 1011 .... ....                                            @param44
 
 ### Integer Comparison
-
 CMPB_imm4_16  0101 0000 .... ....                                            @param44_cmp_imm
 CMPB_reg      0101 0001 .... ....                                            @param44_cmp
 CMPD_imm32    0000 0000 1001 ....  .... .... .... ....  .... .... .... ....  @param4_32
@@ -77,6 +76,14 @@ CMPD_reg      0101 0111 .... ....                                            @pa
 CMPW_imm4_16  0101 0010 .... ....                                            @param44_cmp_imm
 CMPW_reg      0101 0011 .... ....                                            @param44_cmp
 
+### Logical and Boolean
+ANDB_imm4_16  0010 0000 .... ....                                            @param44_imm
+ANDB_reg      0010 0001 .... ....                                            @param44
+ANDW_imm4_16  0010 0010 .... ....                                            @param44_imm
+ANDW_reg      0010 0011 .... ....                                            @param44
+ANDD_imm32    0000 0000 0100 ....  .... .... .... ....  .... .... .... ....  @param4_32
+ANDD_rp       0000 0000 0001 0100  1011 ---- .... ....                       @escape2_dc
+
 ### Jumps and Linkeage
 
 BRCOND_disp8  0001 .... .... ....  @param84
diff --git a/target/cr16c/translate.c b/target/cr16c/translate.c
index 6327a4d4bb..1b38836323 100644
--- a/target/cr16c/translate.c
+++ b/target/cr16c/translate.c
@@ -809,6 +809,45 @@ static bool trans_CMPW_reg(DisasContext *ctx, arg_CMPW_reg *a) {
     return true;
 }
 
+
+/* Logical and Boolean */
+
+static bool trans_ANDB_imm4_16(DisasContext *ctx, arg_ANDB_imm4_16 *a) {
+    uint16_t imm = get_imm4(ctx, a->imm) | 0xFF00;
+    tcg_gen_andi_i32(r[a->rd], r[a->rd], imm);
+    return true;
+}
+
+static bool trans_ANDB_reg(DisasContext *ctx, arg_ANDB_reg *a) {
+    TCGv_i32 temp = tcg_temp_new_i32();
+    tcg_gen_ori_i32(temp, r[a->rs], 0xFF00);
+    tcg_gen_and_i32(r[a->rd], temp, r[a->rd]);
+    return true;
+}
+
+static bool trans_ANDW_imm4_16(DisasContext *ctx, arg_ANDW_imm4_16 *a) {
+    uint16_t imm = get_imm4(ctx, a->imm);
+    tcg_gen_andi_i32(r[a->rd], r[a->rd], imm);
+    return true;
+}
+
+static bool trans_ANDW_reg(DisasContext *ctx, arg_ANDW_reg *a) {
+    tcg_gen_and_i32(r[a->rd], r[a->rd], r[a->rs]);
+    return true;
+}
+
+static bool trans_ANDD_imm32(DisasContext *ctx, arg_ANDD_imm32 *a) {
+    tcg_gen_andi_i32(r[a->rd], r[a->rd], a->imm);
+    tcg_gen_andi_i32(r[a->rd+1], r[a->rd+1], a->imm >> 16);
+    return true;
+}
+
+static bool trans_ANDD_rp(DisasContext *ctx, arg_ANDD_rp *a) {
+    tcg_gen_and_i32(r[a->rd], r[a->rd], r[a->rs]);
+    tcg_gen_and_i32(r[a->rd+1], r[a->rd+1], r[a->rs+1]);
+    return true;
+}
+
 /* Jumps and Linkage */
 
 /* For now this instruction is abused as semihosting instruction for tests */
diff --git a/tests/tcg/cr16c/test05-logic.S b/tests/tcg/cr16c/test05-logic.S
new file mode 100644
index 0000000000..237e41f93e
--- /dev/null
+++ b/tests/tcg/cr16c/test05-logic.S
@@ -0,0 +1,84 @@
+#include "macros.inc"
+
+.global _start
+
+.text
+_start:
+	/* Initialize registers */
+	RESET
+
+	/*** ANDB imm4/16 ***/
+	andb $0x00FF, r11
+	EXPECT 0x000B, r11
+	andb $0x9900, r10
+	EXPECT 0x0100, r10
+	andb $0x0055, r9
+	EXPECT 0x0201, r9
+	RESET
+
+
+	/*** ANDB reg ***/
+	movw $0x22FF, r2
+	andb r2, r3
+	EXPECT 0x0803, r3
+	andb r0, r1
+	EXPECT 0x0A00, r1
+	andb r4, r7
+	EXPECT 0x0404, r7
+	RESET
+
+
+	/*** ANDW imm4/16 ***/
+	andw $0xFFFF, r11
+	EXPECT 0x000B, r11
+	andw $0x0000, r10
+	EXPECT 0x0000, r10
+	andw $0x5555, r9
+	EXPECT 0x0001, r9
+	RESET
+
+
+	/*** ANDW reg ***/
+	movw $-1, r2
+	andw r2, r3
+	EXPECT 0x0803, r3
+	movw $0, r2
+	andw r2, r1
+	EXPECT 0x0000, r1
+	andw r4, r7
+	EXPECT 0x0404, r7
+	RESET
+
+
+	/*** ANDD imm4/16 ***/
+	andd $0xFFFFFFFF, (r11,r10)
+	EXPECT 0x010A, r10
+	EXPECT 0x000B, r11
+	andd $0x00000000, (r9,r8)
+	EXPECT 0x0000, r8
+	EXPECT 0x0000, r9
+	andd $0x55555555, (r7,r6)
+	EXPECT 0x0504, r6
+	EXPECT 0x0405, r7
+	RESET
+
+
+	/*** ANDD rp ***/
+	movw $-1, r0
+	movw $-1, r1
+	andd (r1,r0), (r3,r2)
+	EXPECT 0x0902, r2
+	EXPECT 0x0803, r3
+	movw $0, r0
+	movw $0, r1
+	andd (r1,r0), (r6,r5)
+	EXPECT 0, r5
+	EXPECT 0, r6
+	andd (r10,r9), (r8,r7)
+	EXPECT 0x0001, r7
+	EXPECT 0x0108, r8
+	RESET
+
+
+	ENDING
+	FAIL_HANDLER