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target/arm: Split out gen_wrap2_i32 helper

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Wrapper to extract the low 32 bits, perform an operation,
and zero-extend back to 64 bits.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20250803014019.416797-5-richard.henderson@linaro.org
[PMM: fixed wrong output-reg argument in callsites; add comment]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2025-08-26 11:21:29 +01:00 • committed by Peter Maydell
parent 506538208d
commit 8a4bb8b975
1 changed files with 15 additions and 10 deletions
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25
target/arm/tcg/translate-a64.c
View file

@ -8231,13 +8231,22 @@ static bool gen_rr(DisasContext *s, int rd, int rn, ArithOneOp fn)
return true;
}
/*
* Perform 32-bit operation fn on the low half of n;
* the high half of the output is zeroed.
*/
static void gen_wrap2_i32(TCGv_i64 d, TCGv_i64 n, NeonGenOneOpFn fn)
{
TCGv_i32 t = tcg_temp_new_i32();
tcg_gen_extrl_i64_i32(t, n);
fn(t, t);
tcg_gen_extu_i32_i64(d, t);
}
static void gen_rbit32(TCGv_i64 tcg_rd, TCGv_i64 tcg_rn)
{
TCGv_i32 t32 = tcg_temp_new_i32();
tcg_gen_extrl_i64_i32(t32, tcg_rn);
gen_helper_rbit(t32, t32);
tcg_gen_extu_i32_i64(tcg_rd, t32);
gen_wrap2_i32(tcg_rd, tcg_rn, gen_helper_rbit);
}
static void gen_rev16_xx(TCGv_i64 tcg_rd, TCGv_i64 tcg_rn, TCGv_i64 mask)
@ -8293,11 +8302,7 @@ static void gen_clz64(TCGv_i64 tcg_rd, TCGv_i64 tcg_rn)
static void gen_cls32(TCGv_i64 tcg_rd, TCGv_i64 tcg_rn)
{
TCGv_i32 t32 = tcg_temp_new_i32();
tcg_gen_extrl_i64_i32(t32, tcg_rn);
tcg_gen_clrsb_i32(t32, t32);
tcg_gen_extu_i32_i64(tcg_rd, t32);
gen_wrap2_i32(tcg_rd, tcg_rn, tcg_gen_clrsb_i32);
}
TRANS(CLZ, gen_rr, a->rd, a->rn, a->sf ? gen_clz64 : gen_clz32)