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hw/arm/xlnx-versal: gem: refactor creation

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Refactor the GEM ethernet controllers creation using the VersalMap
structure.

Note that the connection to the CRL is removed for now and will be
re-added by next commits.

The FDT nodes are created in reverse order compared to the devices
creation to keep backward compatibility with the previous generated
FDTs.

Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20250926070806.292065-7-luc.michel@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Luc Michel 2025-09-26 09:07:24 +02:00 • committed by Peter Maydell
parent b392177e42
commit 8aaeb96405
3 changed files with 116 additions and 96 deletions
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3
include/hw/arm/xlnx-versal.h
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@ -18,7 +18,6 @@
#include "hw/or-irq.h"
#include "hw/intc/arm_gicv3.h"
#include "hw/dma/xlnx-zdma.h"
#include "hw/net/cadence_gem.h"
#include "hw/rtc/xlnx-zynqmp-rtc.h"
#include "qom/object.h"
#include "hw/usb/xlnx-usb-subsystem.h"
@ -78,8 +77,6 @@ struct Versal {
MemoryRegion mr_ocm;
struct {
CadenceGEMState gem[XLNX_VERSAL_NR_GEMS];
OrIRQState gem_irq_orgate[XLNX_VERSAL_NR_GEMS];
XlnxZDMA adma[XLNX_VERSAL_NR_ADMAS];
VersalUsb2 usb;
} iou;