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hw/arm/aspeed: Remove AspeedSoCState dependency from aspeed_soc_uart_set_chr() API

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Refactor the aspeed_soc_uart_set_chr() helper to remove its dependency
on AspeedSoCState and make the UART character device binding more
generic.

The function now takes SerialMM *uart, uarts_base, and uarts_num
as arguments instead of relying on AspeedSoCState. All affected call
sites in aspeed.c, aspeed_ast27x0-fc.c, and fby35.c are updated
to use the new parameter format.

This improves API flexibility and enables reuse across different Aspeed
SoC variants without requiring access to internal SoC state.

No functional change.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20251013054334.955331-4-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
This commit is contained in:
Jamin Lin 2025-10-13 13:43:15 +08:00 • committed by Cédric Le Goater
parent 37d2e4b533
commit 8f1ceec735
5 changed files with 29 additions and 13 deletions
Download patch file Download diff file Expand all files Collapse all files

6
hw/arm/aspeed.c
View file

@ -299,12 +299,14 @@ static void connect_serial_hds_to_uarts(AspeedMachineState *bmc)
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default;
aspeed_soc_uart_set_chr(s, uart_chosen, serial_hd(0));
aspeed_soc_uart_set_chr(s->uart, uart_chosen, sc->uarts_base,
sc->uarts_num, serial_hd(0));
for (int i = 1, uart = sc->uarts_base; i < sc->uarts_num; uart++) {
if (uart == uart_chosen) {
continue;
}
aspeed_soc_uart_set_chr(s, uart, serial_hd(i++));
aspeed_soc_uart_set_chr(s->uart, uart, sc->uarts_base, sc->uarts_num,
serial_hd(i++));
}
}

13
hw/arm/aspeed_ast27x0-fc.c
View file

@ -91,7 +91,8 @@ static bool ast2700fc_ca35_init(MachineState *machine, Error **errp)
AST2700FC_HW_STRAP1, &error_abort);
object_property_set_int(OBJECT(&s->ca35), "hw-strap2",
AST2700FC_HW_STRAP2, &error_abort);
aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART12, serial_hd(0));
aspeed_soc_uart_set_chr(soc->uart, ASPEED_DEV_UART12, sc->uarts_base,
sc->uarts_num, serial_hd(0));
if (!qdev_realize(DEVICE(&s->ca35), NULL, errp)) {
return false;
}
@ -115,6 +116,7 @@ static bool ast2700fc_ca35_init(MachineState *machine, Error **errp)
static bool ast2700fc_ssp_init(MachineState *machine, Error **errp)
{
AspeedSoCState *soc;
AspeedSoCClass *sc;
Ast2700FCState *s = AST2700A1FC(machine);
s->ssp_sysclk = clock_new(OBJECT(s), "SSP_SYSCLK");
clock_set_hz(s->ssp_sysclk, 200000000ULL);
@ -128,7 +130,9 @@ static bool ast2700fc_ssp_init(MachineState *machine, Error **errp)
OBJECT(&s->ssp_memory), &error_abort);
soc = ASPEED_SOC(&s->ssp);
aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART4, serial_hd(1));
sc = ASPEED_SOC_GET_CLASS(soc);
aspeed_soc_uart_set_chr(soc->uart, ASPEED_DEV_UART4, sc->uarts_base,
sc->uarts_num, serial_hd(1));
if (!qdev_realize(DEVICE(&s->ssp), NULL, errp)) {
return false;
}
@ -139,6 +143,7 @@ static bool ast2700fc_ssp_init(MachineState *machine, Error **errp)
static bool ast2700fc_tsp_init(MachineState *machine, Error **errp)
{
AspeedSoCState *soc;
AspeedSoCClass *sc;
Ast2700FCState *s = AST2700A1FC(machine);
s->tsp_sysclk = clock_new(OBJECT(s), "TSP_SYSCLK");
clock_set_hz(s->tsp_sysclk, 200000000ULL);
@ -152,7 +157,9 @@ static bool ast2700fc_tsp_init(MachineState *machine, Error **errp)
OBJECT(&s->tsp_memory), &error_abort);
soc = ASPEED_SOC(&s->tsp);
aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART7, serial_hd(2));
sc = ASPEED_SOC_GET_CLASS(soc);
aspeed_soc_uart_set_chr(soc->uart, ASPEED_DEV_UART7, sc->uarts_base,
sc->uarts_num, serial_hd(2));
if (!qdev_realize(DEVICE(&s->tsp), NULL, errp)) {
return false;
}

10
hw/arm/aspeed_soc_common.c
View file

@ -59,15 +59,15 @@ bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp)
return true;
}
void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr)
void aspeed_soc_uart_set_chr(SerialMM *uart, int dev, int uarts_base,
int uarts_num, Chardev *chr)
{
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
int uart_first = aspeed_uart_first(sc->uarts_base);
int uart_first = aspeed_uart_first(uarts_base);
int uart_index = aspeed_uart_index(dev);
int i = uart_index - uart_first;
g_assert(0 <= i && i < ARRAY_SIZE(s->uart) && i < sc->uarts_num);
qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr);
g_assert(0 <= i && i < ASPEED_UARTS_NUM && i < uarts_num);
qdev_prop_set_chr(DEVICE(&uart[i]), "chardev", chr);
}
/*

10
hw/arm/fby35.c
View file

@ -71,9 +71,11 @@ static void fby35_bmc_write_boot_rom(DriveInfo *dinfo, MemoryRegion *mr,
static void fby35_bmc_init(Fby35State *s)
{
AspeedSoCState *soc;
AspeedSoCClass *sc;
object_initialize_child(OBJECT(s), "bmc", &s->bmc, "ast2600-a3");
soc = ASPEED_SOC(&s->bmc);
sc = ASPEED_SOC_GET_CLASS(soc);
memory_region_init(&s->bmc_memory, OBJECT(&s->bmc), "bmc-memory",
UINT64_MAX);
@ -91,7 +93,8 @@ static void fby35_bmc_init(Fby35State *s)
&error_abort);
object_property_set_int(OBJECT(&s->bmc), "hw-strap2", 0x00000003,
&error_abort);
aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART5, serial_hd(0));
aspeed_soc_uart_set_chr(soc->uart, ASPEED_DEV_UART5, sc->uarts_base,
sc->uarts_num, serial_hd(0));
qdev_realize(DEVICE(&s->bmc), NULL, &error_abort);
aspeed_board_init_flashes(&soc->fmc, "n25q00", 2, 0);
@ -118,12 +121,14 @@ static void fby35_bmc_init(Fby35State *s)
static void fby35_bic_init(Fby35State *s)
{
AspeedSoCState *soc;
AspeedSoCClass *sc;
s->bic_sysclk = clock_new(OBJECT(s), "SYSCLK");
clock_set_hz(s->bic_sysclk, 200000000ULL);
object_initialize_child(OBJECT(s), "bic", &s->bic, "ast1030-a1");
soc = ASPEED_SOC(&s->bic);
sc = ASPEED_SOC_GET_CLASS(soc);
memory_region_init(&s->bic_memory, OBJECT(&s->bic), "bic-memory",
UINT64_MAX);
@ -131,7 +136,8 @@ static void fby35_bic_init(Fby35State *s)
qdev_connect_clock_in(DEVICE(&s->bic), "sysclk", s->bic_sysclk);
object_property_set_link(OBJECT(&s->bic), "memory", OBJECT(&s->bic_memory),
&error_abort);
aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART5, serial_hd(1));
aspeed_soc_uart_set_chr(soc->uart, ASPEED_DEV_UART5, sc->uarts_base,
sc->uarts_num, serial_hd(1));
qdev_realize(DEVICE(&s->bic), NULL, &error_abort);
aspeed_board_init_flashes(&soc->fmc, "sst25vf032b", 2, 2);

3
include/hw/arm/aspeed_soc.h
View file

@ -306,7 +306,8 @@ enum {
qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev);
bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp);
void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr);
void aspeed_soc_uart_set_chr(SerialMM *uart, int dev, int uarts_base,
int uarts_num, Chardev *chr);
bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp);
void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr);
void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,