ppc/pnv: Add PHB5 PCIe Host bridge to Power11
Power11 also uses PHB5, same as Power10. Add Power11 PHBs with similar code as the corresponding Power10 implementation. Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Aditya Gupta <adityag@linux.ibm.com> Tested-by: Amit Machhiwal <amachhiw@linux.ibm.com> Tested-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Link: https://lore.kernel.org/r/20250925173049.891406-6-adityag@linux.ibm.com Message-ID: <20250925173049.891406-6-adityag@linux.ibm.com>
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1 changed files with 56 additions and 1 deletions
57
hw/ppc/pnv.c
57
hw/ppc/pnv.c
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@ -978,6 +978,8 @@ static void pnv_chip_power11_pic_print_info(PnvChip *chip, GString *buf)
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pnv_xive2_pic_print_info(&chip11->xive, buf);
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pnv_psi_pic_print_info(&chip11->psi, buf);
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object_child_foreach_recursive(OBJECT(chip),
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pnv_chip_power9_pic_print_info_child, buf);
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}
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/* Always give the first 1GB to chip 0 else we won't boot */
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@ -2473,6 +2475,7 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
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static void pnv_chip_power11_instance_init(Object *obj)
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{
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PnvChip *chip = PNV_CHIP(obj);
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Pnv11Chip *chip11 = PNV11_CHIP(obj);
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PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
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int i;
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@ -2495,6 +2498,13 @@ static void pnv_chip_power11_instance_init(Object *obj)
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object_initialize_child(obj, "n1-chiplet", &chip11->n1_chiplet,
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TYPE_PNV_N1_CHIPLET);
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chip->num_pecs = pcc->num_pecs;
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for (i = 0; i < chip->num_pecs; i++) {
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object_initialize_child(obj, "pec[*]", &chip11->pecs[i],
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TYPE_PNV_PHB5_PEC);
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}
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for (i = 0; i < pcc->i2c_num_engines; i++) {
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object_initialize_child(obj, "i2c[*]", &chip11->i2c[i], TYPE_PNV_I2C);
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}
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@ -2527,6 +2537,38 @@ static void pnv_chip_power11_quad_realize(Pnv11Chip *chip11, Error **errp)
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}
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}
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static void pnv_chip_power11_phb_realize(PnvChip *chip, Error **errp)
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{
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Pnv11Chip *chip11 = PNV11_CHIP(chip);
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int i;
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for (i = 0; i < chip->num_pecs; i++) {
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PnvPhb4PecState *pec = &chip11->pecs[i];
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PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
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uint32_t pec_cplt_base;
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uint32_t pec_nest_base;
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uint32_t pec_pci_base;
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object_property_set_int(OBJECT(pec), "index", i, &error_fatal);
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object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id,
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&error_fatal);
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object_property_set_link(OBJECT(pec), "chip", OBJECT(chip),
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&error_fatal);
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if (!qdev_realize(DEVICE(pec), NULL, errp)) {
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return;
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}
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pec_cplt_base = pecc->xscom_cplt_base(pec);
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pec_nest_base = pecc->xscom_nest_base(pec);
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pec_pci_base = pecc->xscom_pci_base(pec);
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pnv_xscom_add_subregion(chip, pec_cplt_base,
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&pec->nest_pervasive.xscom_ctrl_regs_mr);
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pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr);
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pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr);
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}
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}
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static void pnv_chip_power11_realize(DeviceState *dev, Error **errp)
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{
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PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
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@ -2664,7 +2706,12 @@ static void pnv_chip_power11_realize(DeviceState *dev, Error **errp)
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pnv_xscom_add_subregion(chip, PNV11_XSCOM_N1_PB_SCOM_ES_BASE,
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&chip11->n1_chiplet.xscom_pb_es_mr);
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/* WIP: PHB added in future patch */
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/* PHBs */
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pnv_chip_power11_phb_realize(chip, &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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}
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/*
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* I2C
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@ -2799,6 +2846,7 @@ static void pnv_chip_power11_class_init(ObjectClass *klass, const void *data)
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k->xscom_core_base = pnv_chip_power11_xscom_core_base;
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k->xscom_pcba = pnv_chip_power11_xscom_pcba;
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dc->desc = "PowerNV Chip Power11";
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k->num_pecs = PNV10_CHIP_MAX_PEC;
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k->i2c_num_engines = PNV10_CHIP_MAX_I2C;
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k->i2c_ports_per_engine = i2c_ports_per_engine;
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@ -3365,6 +3413,13 @@ static void pnv_machine_power11_class_init(ObjectClass *oc, const void *data)
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XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
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static const char compat[] = "qemu,powernv11\0ibm,powernv";
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static GlobalProperty phb_compat[] = {
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{ TYPE_PNV_PHB, "version", "5" },
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{ TYPE_PNV_PHB_ROOT_PORT, "version", "5" },
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};
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compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat));
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pmc->compat = compat;
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pmc->compat_size = sizeof(compat);
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pmc->max_smt_threads = 4;
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