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CR16C: Fix abs24 and disp20 rel load/stor insns

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This commit is contained in:
Jonas Bewig 2026-04-22 22:52:12 +02:00
parent c3d65261db
commit 92b96a26c8
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GPG key ID: 8D99867797A4886F
3 changed files with 100 additions and 17 deletions
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63
tests/tcg/cr16c/testxx-loads.S
View file

@ -60,8 +60,22 @@ _start:
EXPECTD 0x12345603, r12
RESET
/* Relocation, abs20 rel and abs24 tests not implemented yet because of
some unclear behavior in gnu assembler we need to look at */
/* LOADB abs20 rel */
movd $0xFF00, (r12)
loadb [r12]0xF4, r1
EXPECT 0x0A04, r1
loadb [r12]0xF5, r13
EXPECTD 0x87654305, r13
RESET
/* LOADB abs24 */
storb $3, 0xEEFFF3
storb $4, 0xEEFFF4
loadb 0xEEFFF3, r0
EXPECT 0x0B03, r0
loadb 0xEEFFF4, r13
EXPECTD 0x87654304, r13
RESET
/*** 16 BIT ***/
@ -116,8 +130,24 @@ _start:
EXPECTD 0x12340403, r12
RESET
/* Relocation, abs20 rel and abs24 tests not implemented yet because of
some unclear behavior in gnu assembler we need to look at */
/* LOADW abs20 rel */
movd $0xFF00, (r12)
loadw [r12]0xF4, r1
EXPECT 0x0504, r1
loadw [r12]0xF6, r13
EXPECTD 0x87650706, r13
RESET
/* LOADW abs24 */
storb $3, 0xEEFFF3
storb $4, 0xEEFFF4
storb $5, 0xEEFFF5
storb $6, 0xEEFFF6
loadw 0xEEFFF3, r0
EXPECT 0x0403, r0
loadw 0xEEFFF5, r13
EXPECTD 0x87650605, r13
RESET
/*** 32 BIT ***/
@ -177,8 +207,29 @@ _start:
EXPECTD 0x05040302, r12
RESET
/* Relocation, abs20 rel and abs24 tests not implemented yet because of
some unclear behavior in gnu assembler we need to look at */
/* LOADD abs20 rel */
movd $0xFF00, (r12)
loadd [r12]0xF4, (r1,r0)
EXPECT 0x0504, r0
EXPECT 0x0706, r1
loadd [r12]0xF0, (r13)
EXPECTD 0x03020100, r13
RESET
/* LOADD abs24 */
storb $0, 0xEEFFF0
storb $1, 0xEEFFF1
storb $2, 0xEEFFF2
storb $3, 0xEEFFF3
storb $4, 0xEEFFF4
storb $5, 0xEEFFF5
storb $6, 0xEEFFF6
loadd 0xEEFFF3, (r1,r0)
EXPECT 0x0403, r0
EXPECT 0x0605, r1
loadd 0xEEFFF0, (r13)
EXPECTD 0x03020100, r13
RESET
/*** LOADM(P) ***/

52
tests/tcg/cr16c/testxy-stors.S
View file

@ -50,14 +50,22 @@ _start:
EXPECTM 0x0502, 0xFFF4
RESET
/* STORB rrp abs20 */
/* STORB abs20 rel */
movd $0xFFF0, (r12)
storb r2, [r12]1
EXPECTM 0x0202, 0xFFF1
RESET
/* STORB abs24 */
/* TODO */
storb $0x0, 0xEEFFF0
storb $0x1, 0xEEFFF1
storb $0x2, 0xEEFFF2
storb $0x3, 0xEEFFF3
storb r0, 0xEEFFF2
EXPECTM 0x0300, 0xEEFFF2
storb r12, 0xEEFFF0
EXPECTM 0x0178, 0xEEFFF0
RESET
/* STORB rrp disp14 imm */
movd $0x4, (r12)
@ -104,7 +112,10 @@ _start:
RESET
/* STORB abs24 imm */
/* TODO */
storb $0x2, 0xEEFFF0
storb $0x3, 0xEEFFF1
EXPECTM 0x302, 0xEEFFF0
RESET
/*** 16 BIT ***/
@ -149,14 +160,22 @@ _start:
EXPECTM 0x0902, 0xFFF4
RESET
/* STORW rrp abs20 */
/* STORW abs20 rel */
movd $0xFFF0, (r12)
storw r2, [r12]1
EXPECTM 0x0902, 0xFFF1
RESET
/* STORW rrp abs24 */
/* TODO */
/* STORW abs24 */
storb $0x0, 0xEEFFF0
storb $0x1, 0xEEFFF1
storb $0x2, 0xEEFFF2
storb $0x3, 0xEEFFF3
storw r0, 0xEEFFF2
EXPECTM 0x0B00, 0xEEFFF2
storw r12, 0xEEFFF0
EXPECTM 0x5678, 0xEEFFF0
RESET
/* STORW rrp disp14 imm */
movd $0x4, (r12)
@ -203,7 +222,10 @@ _start:
RESET
/* STORW abs24 imm */
/* TODO */
storw $0x1, 0xEEFFF1
storw $0x2, 0xEEFFF0
EXPECTM 0x2, 0xEEFFF0
RESET
/*** 32 BIT ***/
@ -254,15 +276,25 @@ _start:
EXPECTM 0x0803, 0xFFF6
RESET
/* STORD rrp abs20 */
/* STORD abs20 rel */
movd $0xFFF0, (r12)
stord (r3,r2), [r12]1
EXPECTM 0x0902, 0xFFF1
EXPECTM 0x0803, 0xFFF3
RESET
/* STORD rrp abs24 */
/* TODO */
/* STORD abs24 */
storb $0x0, 0xEEFFF0
storb $0x1, 0xEEFFF1
storb $0x2, 0xEEFFF2
storb $0x3, 0xEEFFF3
stord (r1,r0), 0xEEFFF0
EXPECTM 0x0B00, 0xEEFFF0
EXPECTM 0x0A01, 0xEEFFF2
stord (r12), 0xEEFFF0
EXPECTM 0x5678, 0xEEFFF0
EXPECTM 0x1234, 0xEEFFF2
RESET
/*** STORM(P) ***/